Nicolas Pitre 94f39e5a80 riscv: fix wrong access width in assembly code ... The thread->base.user_options field is an uint8_t. Access it using lb. A "copy" of it is made into __esf.fp_state. Make that field an uint8_t too and access it with lb/sb. _callee_saved.fcsr is an uint32_t. Access it with lw/sw. Ditto for is_user_mode. Signed-off-by: Nicolas Pitre <npitre@baylibre.com>		2022-03-21 07:28:05 -04:00
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offsets	Revert "arch/riscv: Get current CPU properly instead of assuming single CPU"	2022-03-21 07:28:05 -04:00
pmp	everywhere: fix typos	2022-03-18 13:24:08 -04:00
CMakeLists.txt	Revert "arch/riscv: Use arch_switch() for context swap"	2022-03-21 07:28:05 -04:00
coredump.c	coredump: add support for RISC-V	2021-12-08 08:54:32 -05:00
cpu_idle.c	riscv: use standard MSTATUS	2020-01-06 13:27:45 -05:00
fatal.c	arch: riscv: pmp: Fix 64-bit compatibility of pointer size	2022-01-18 13:11:36 -05:00
irq_manage.c	kernel: Cleanup logger setup in kernel files	2020-11-27 09:56:34 -05:00
irq_offload.c	Revert "arch/riscv: Do not use irq_lock() on arch_irq_offload"	2022-03-21 07:28:05 -04:00
isr.S	riscv: fix wrong access width in assembly code	2022-03-21 07:28:05 -04:00
prep_c.c	core: z_data_copy does not depend on CONFIG_XIP	2022-02-22 10:22:53 +01:00
reboot.c	riscv: remove @return doc for void functions	2022-01-12 16:02:16 -05:00
reset.S	riscv: use simplest asm expression when possible	2022-03-21 07:28:05 -04:00
smp.c	arch/riscv: Add IPI support	2022-02-25 19:13:50 -05:00
swap.S	riscv: use simplest asm expression when possible	2022-03-21 07:28:05 -04:00
thread.c	Revert "arch/riscv: Use arch_switch() for context swap"	2022-03-21 07:28:05 -04:00
tls.c	riscv: add support for thread local storage	2020-10-24 10:52:00 -07:00
userspace.S	arch: riscv: add memory protection support	2020-11-09 15:37:11 -05:00