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zephyr/arch/riscv/core
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Jim Shu 1b4dad433f arch: riscv: enable FPU of threads in unshared FP mode 
In unshared FP mode, only 1 thread can use FPU but kernel doesn't know
which one, so riscv arch would enable FPU of each thread.

Signed-off-by: Jim Shu <cwshu@andestech.com>
2021-06-08 11:47:02 -05:00
..
offsets arch: riscv: add memory protection support 2020-11-09 15:37:11 -05:00
pmp arch: riscv: Fix 10.4 violations 2021-04-10 09:59:37 -04:00
CMakeLists.txt arch: riscv: add common stub reboot function 2021-03-04 11:09:51 -06:00
cpu_idle.c riscv: use standard MSTATUS 2020-01-06 13:27:45 -05:00
fatal.c riscv: MTVAL CSR not supported on OpenISA RV32M1 2021-04-08 14:22:54 +02:00
irq_manage.c kernel: Cleanup logger setup in kernel files 2020-11-27 09:56:34 -05:00
irq_offload.c arch: Apply IRQ offload API change 2020-09-02 13:48:13 +02:00
isr.S tracing: roll thread switch in/out into thread stats functions 2020-11-11 23:55:49 -05:00
prep_c.c arch: riscv: add memory protection support 2020-11-09 15:37:11 -05:00
reboot.c arch: riscv: add common stub reboot function 2021-03-04 11:09:51 -06:00
reset.S arch: riscv: add memory protection support 2020-11-09 15:37:11 -05:00
swap.S benchmarking: remove execution benchmarking code 2020-09-05 13:28:38 -05:00
thread.c arch: riscv: enable FPU of threads in unshared FP mode 2021-06-08 11:47:02 -05:00
tls.c riscv: add support for thread local storage 2020-10-24 10:52:00 -07:00
userspace.S arch: riscv: add memory protection support 2020-11-09 15:37:11 -05:00