riscv: MTVAL CSR not supported on OpenISA RV32M1
Don't report MTVAL on the OpenISA RV32M1 SoC as this CSR isn't supported on the SoC. Fixes: #34014 Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
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1 changed files with 7 additions and 1 deletions
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@ -103,15 +103,21 @@ void _Fault(z_arch_esf_t *esf)
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}
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}
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#endif /* CONFIG_USERSPACE */
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ulong_t mcause, mtval;
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ulong_t mcause;
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__asm__ volatile("csrr %0, mcause" : "=r" (mcause));
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#ifndef CONFIG_SOC_OPENISA_RV32M1_RISCV32
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ulong_t mtval;
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__asm__ volatile("csrr %0, mtval" : "=r" (mtval));
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#endif
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mcause &= SOC_MCAUSE_EXP_MASK;
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LOG_ERR("");
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LOG_ERR(" mcause: %ld, %s", mcause, cause_str(mcause));
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#ifndef CONFIG_SOC_OPENISA_RV32M1_RISCV32
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LOG_ERR(" mtval: %lx", mtval);
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#endif
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z_riscv_fatal_error(K_ERR_CPU_EXCEPTION, esf);
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}
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