Mark Holden 7803a4e590 arch: riscv: ARCH_EXCEPT macro ... Enable ARCH_EXCEPT macro for non-usermode scenario for RISC-V Macro will now raise an illegal instruction exception so that mepc will hold expected value in exception handler, and generated coredump can reconstruct the failing stack Coredump tests running on renode (for RISC-V) can now utilize fatal error path through k_panic Signed-off-by: Mark Holden <mholden@fb.com>		2022-01-01 07:38:20 -05:00
..
offsets	arch: riscv: remove unneeded context switch to gp register	2021-08-18 05:18:55 -04:00
pmp	kernel: mem_domain: arch_mem_domain functions to return errors	2021-11-22 12:45:22 -05:00
CMakeLists.txt	coredump: add support for RISC-V	2021-12-08 08:54:32 -05:00
coredump.c	coredump: add support for RISC-V	2021-12-08 08:54:32 -05:00
cpu_idle.c
fatal.c	arch: riscv: ARCH_EXCEPT macro	2022-01-01 07:38:20 -05:00
irq_manage.c	kernel: Cleanup logger setup in kernel files	2020-11-27 09:56:34 -05:00
irq_offload.c	arch: Apply IRQ offload API change	2020-09-02 13:48:13 +02:00
isr.S	riscv: Don't reschedule on back-to-back interrupts	2021-09-03 12:20:03 -04:00
prep_c.c	arch: riscv: add memory protection support	2020-11-09 15:37:11 -05:00
reboot.c	arch: riscv: add common stub reboot function	2021-03-04 11:09:51 -06:00
reset.S	arch: riscv: add memory protection support	2020-11-09 15:37:11 -05:00
swap.S	benchmarking: remove execution benchmarking code	2020-09-05 13:28:38 -05:00
thread.c	Revert "arch: riscv: added support for custom initialization of gp register"	2021-08-18 05:18:55 -04:00
tls.c	riscv: add support for thread local storage	2020-10-24 10:52:00 -07:00
userspace.S	arch: riscv: add memory protection support	2020-11-09 15:37:11 -05:00