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zephyr/soc/riscv/riscv-privilege
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Wei-Tai Lee b055e3ca23 soc: riscv: andes_v5: Fix system initialization for L2C 
- Put L2C init level in pre_kernel_2 to wait for syscon driver
- Check if SMU exists when preprocessing

Signed-off-by: Wei-Tai Lee <wtlee@andestech.com>
2022-11-29 09:50:05 +01:00
..
andes_v5 soc: riscv: andes_v5: Fix system initialization for L2C 2022-11-29 09:50:05 +01:00
common soc: riscv: remove usage of SOC_ERET 2022-08-04 13:44:48 +02:00
gd32vf103 include: add missing irq.h include 2022-10-11 18:05:17 +02:00
miv riscv: Introduce Zicsr and Zifencei extensions 2022-08-29 16:57:18 +02:00
mpfs riscv: Introduce Zicsr and Zifencei extensions 2022-08-29 16:57:18 +02:00
neorv32 riscv: Introduce Zicsr and Zifencei extensions 2022-08-29 16:57:18 +02:00
sifive-freedom include: add missing sys/util.h include 2022-10-11 18:05:17 +02:00
starfive_jh71xx riscv: Introduce Zicsr and Zifencei extensions 2022-08-29 16:57:18 +02:00
telink_b91 soc: riscv: telink_b91: Place .init before .vectors section 2022-09-08 10:39:31 +02:00
virt soc: riscv: remove unused RISCV_MTIME(CMP)_BASE and IRQ definitions 2022-08-02 09:12:31 +02:00
CMakeLists.txt riscv32: rename to riscv 2019-08-02 13:54:48 -07:00
Kconfig Kconfig: Introduce RISCV_HAS_CLIC 2022-07-11 14:31:39 +02:00
Kconfig.defconfig kconfig: Clean up header comments and make them consistent 2019-11-04 17:31:27 -05:00
Kconfig.soc kconfig: Clean up header comments and make them consistent 2019-11-04 17:31:27 -05:00