204 lines
6.1 KiB
C
204 lines
6.1 KiB
C
/*
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* Copyright (c) 2013-2014 Wind River Systems, Inc.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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/**
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* @file
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* @brief Exception/interrupt context helpers for Cortex-M CPUs
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*
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* Exception/interrupt context helpers.
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*/
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#ifndef ZEPHYR_ARCH_ARM_INCLUDE_CORTEX_M_EXCEPTION_H_
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#define ZEPHYR_ARCH_ARM_INCLUDE_CORTEX_M_EXCEPTION_H_
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#include <zephyr/arch/cpu.h>
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#ifdef _ASMLANGUAGE
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/* nothing */
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#else
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#include <cmsis_core.h>
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#include <zephyr/arch/arm/exception.h>
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#include <zephyr/irq_offload.h>
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#ifdef __cplusplus
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extern "C" {
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#endif
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#ifdef CONFIG_IRQ_OFFLOAD
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extern volatile irq_offload_routine_t offload_routine;
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#endif
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/* Writes to the AIRCR must be accompanied by a write of the value 0x05FA
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* to the Vector Key field, otherwise the writes are ignored.
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*/
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#define AIRCR_VECT_KEY_PERMIT_WRITE 0x05FAUL
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/*
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* The current executing vector is found in the IPSR register. All
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* IRQs and system exceptions are considered as interrupt context.
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*/
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static ALWAYS_INLINE bool arch_is_in_isr(void)
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{
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return (__get_IPSR()) ? (true) : (false);
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}
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/**
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* @brief Find out if we were in ISR context
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* before the current exception occurred.
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*
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* A function that determines, based on inspecting the current
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* ESF, whether the processor was in handler mode before entering
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* the current exception state (i.e. nested exception) or not.
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*
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* Notes:
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* - The function shall only be called from ISR context.
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* - We do not use ARM processor state flags to determine
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* whether we are in a nested exception; we rely on the
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* RETPSR value stacked on the ESF. Hence, the function
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* assumes that the ESF stack frame has a valid RETPSR
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* value.
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*
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* @param esf the exception stack frame (cannot be NULL)
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* @return true if execution state was in handler mode, before
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* the current exception occurred, otherwise false.
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*/
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static ALWAYS_INLINE bool arch_is_in_nested_exception(const z_arch_esf_t *esf)
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{
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return (esf->basic.xpsr & IPSR_ISR_Msk) ? (true) : (false);
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}
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#if defined(CONFIG_USERSPACE)
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/**
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* @brief Is the thread in unprivileged mode
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*
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* @param esf the exception stack frame (unused)
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* @return true if the current thread was in unprivileged mode
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*/
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static ALWAYS_INLINE bool z_arm_preempted_thread_in_user_mode(const z_arch_esf_t *esf)
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{
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return z_arm_thread_is_in_user_mode();
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}
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#endif
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/**
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* @brief Setup system exceptions
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*
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* Set exception priorities to conform with the BASEPRI locking mechanism.
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* Set PendSV priority to lowest possible.
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*
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* Enable fault exceptions.
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*/
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static ALWAYS_INLINE void z_arm_exc_setup(void)
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{
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/* PendSV is set to lowest priority, regardless of it being used.
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* This is done as the IRQ is always enabled.
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*/
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NVIC_SetPriority(PendSV_IRQn, _EXC_PENDSV_PRIO);
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#ifdef CONFIG_CPU_CORTEX_M_HAS_BASEPRI
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/* Note: SVCall IRQ priority level is left to default (0)
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* for Cortex-M variants without BASEPRI (e.g. ARMv6-M).
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*/
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NVIC_SetPriority(SVCall_IRQn, _EXC_SVC_PRIO);
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#endif
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#ifdef CONFIG_CPU_CORTEX_M_HAS_PROGRAMMABLE_FAULT_PRIOS
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NVIC_SetPriority(MemoryManagement_IRQn, _EXC_FAULT_PRIO);
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NVIC_SetPriority(BusFault_IRQn, _EXC_FAULT_PRIO);
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NVIC_SetPriority(UsageFault_IRQn, _EXC_FAULT_PRIO);
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#if defined(CONFIG_CORTEX_M_DEBUG_MONITOR_HOOK)
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NVIC_SetPriority(DebugMonitor_IRQn, IRQ_PRIO_LOWEST);
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#elif defined(CONFIG_CPU_CORTEX_M_HAS_DWT)
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NVIC_SetPriority(DebugMonitor_IRQn, _EXC_FAULT_PRIO);
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#endif
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#if defined(CONFIG_ARM_SECURE_FIRMWARE)
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NVIC_SetPriority(SecureFault_IRQn, _EXC_FAULT_PRIO);
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#endif /* CONFIG_ARM_SECURE_FIRMWARE */
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/* Enable Usage, Mem, & Bus Faults */
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SCB->SHCSR |= SCB_SHCSR_USGFAULTENA_Msk | SCB_SHCSR_MEMFAULTENA_Msk |
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SCB_SHCSR_BUSFAULTENA_Msk;
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#if defined(CONFIG_ARM_SECURE_FIRMWARE)
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/* Enable Secure Fault */
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SCB->SHCSR |= SCB_SHCSR_SECUREFAULTENA_Msk;
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/* Clear BFAR before setting BusFaults to target Non-Secure state. */
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SCB->BFAR = 0;
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#endif /* CONFIG_ARM_SECURE_FIRMWARE */
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#endif /* CONFIG_CPU_CORTEX_M_HAS_PROGRAMMABLE_FAULT_PRIOS */
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#if defined(CONFIG_ARM_SECURE_FIRMWARE) && \
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!defined(CONFIG_ARM_SECURE_BUSFAULT_HARDFAULT_NMI)
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/* Set NMI, Hard, and Bus Faults as Non-Secure.
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* NMI and Bus Faults targeting the Secure state will
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* escalate to a SecureFault or SecureHardFault.
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*/
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SCB->AIRCR =
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(SCB->AIRCR & (~(SCB_AIRCR_VECTKEY_Msk)))
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| SCB_AIRCR_BFHFNMINS_Msk
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| ((AIRCR_VECT_KEY_PERMIT_WRITE << SCB_AIRCR_VECTKEY_Pos) &
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SCB_AIRCR_VECTKEY_Msk);
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/* Note: Fault conditions that would generate a SecureFault
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* in a PE with the Main Extension instead generate a
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* SecureHardFault in a PE without the Main Extension.
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*/
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#endif /* ARM_SECURE_FIRMWARE && !ARM_SECURE_BUSFAULT_HARDFAULT_NMI */
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#if defined(CONFIG_CPU_CORTEX_M_HAS_SYSTICK) && \
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!defined(CONFIG_CORTEX_M_SYSTICK)
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/* SoC implements SysTick, but the system does not use it
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* as driver for system timing. However, the SysTick IRQ is
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* always enabled, so we must ensure the interrupt priority
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* is set to a level lower than the kernel interrupts (for
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* the assert mechanism to work properly) in case the SysTick
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* interrupt is accidentally raised.
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*/
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NVIC_SetPriority(SysTick_IRQn, _EXC_IRQ_DEFAULT_PRIO);
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#endif /* CPU_CORTEX_M_HAS_SYSTICK && ! CORTEX_M_SYSTICK */
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}
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/**
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* @brief Clear Fault exceptions
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*
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* Clear out exceptions for Mem, Bus, Usage and Hard Faults
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*/
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static ALWAYS_INLINE void z_arm_clear_faults(void)
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{
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#if defined(CONFIG_ARMV6_M_ARMV8_M_BASELINE)
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#elif defined(CONFIG_ARMV7_M_ARMV8_M_MAINLINE)
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/* Reset all faults */
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SCB->CFSR = SCB_CFSR_USGFAULTSR_Msk |
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SCB_CFSR_MEMFAULTSR_Msk |
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SCB_CFSR_BUSFAULTSR_Msk;
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/* Clear all Hard Faults - HFSR is write-one-to-clear */
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SCB->HFSR = 0xffffffff;
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#else
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#error Unknown ARM architecture
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#endif /* CONFIG_ARMV6_M_ARMV8_M_BASELINE */
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}
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/**
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* @brief Assess whether a debug monitor event should be treated as an error
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*
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* This routine checks the status of a debug_monitor() exception, and
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* evaluates whether this needs to be considered as a processor error.
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*
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* @return true if the DM exception is a processor error, otherwise false
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*/
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bool z_arm_debug_monitor_event_error_check(void);
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#ifdef __cplusplus
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}
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#endif
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#endif /* _ASMLANGUAGE */
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#endif /* ZEPHYR_ARCH_ARM_INCLUDE_CORTEX_M_EXCEPTION_H_ */
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