It doesn't make sense to keep the aarch32 directory in the 'arch/arm/core' directory as the aarch64 has been moved out. This commit introduces the following major changes. 1. Move all directories and files in 'arch/arm/core/aarch32' to 'arch/arm/core' and remove the 'arch/arm/core/aarch32' directory. 2. Move all directories and files in 'arch/include/aarch32' to 'arch/include' and remove the 'arch/include/aarch32' directory. 3. Remove the nested including in the 'arch/include/kernel_arch_func.h' and 'arch/include/offsets_short_arch.h' header files. 4. Change the path string which is influenced by the changement 1 and 2. Signed-off-by: Huifeng Zhang <Huifeng.Zhang@arm.com>
204 lines
5.6 KiB
C
204 lines
5.6 KiB
C
/*
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* ARMv7 MMU support
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*
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* Private data declarations
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*
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* Copyright (c) 2021 Weidmueller Interface GmbH & Co. KG
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* SPDX-License-Identifier: Apache-2.0
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*/
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#ifndef ZEPHYR_ARCH_AARCH32_ARM_MMU_PRIV_H_
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#define ZEPHYR_ARCH_AARCH32_ARM_MMU_PRIV_H_
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/*
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* Comp.:
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* ARM Architecture Reference Manual, ARMv7-A and ARMv7-R edition
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* ARM document ID DDI0406C Rev. d, March 2018
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* L1 / L2 page table entry formats and entry type IDs:
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* Chapter B3.5.1, fig. B3-4 and B3-5, p. B3-1323 f.
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*/
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#define ARM_MMU_PT_L1_NUM_ENTRIES 4096
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#define ARM_MMU_PT_L2_NUM_ENTRIES 256
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#define ARM_MMU_PTE_L1_INDEX_PA_SHIFT 20
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#define ARM_MMU_PTE_L1_INDEX_MASK 0xFFF
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#define ARM_MMU_PTE_L2_INDEX_PA_SHIFT 12
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#define ARM_MMU_PTE_L2_INDEX_MASK 0xFF
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#define ARM_MMU_PT_L2_ADDR_SHIFT 10
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#define ARM_MMU_PT_L2_ADDR_MASK 0x3FFFFF
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#define ARM_MMU_PTE_L2_SMALL_PAGE_ADDR_SHIFT 12
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#define ARM_MMU_PTE_L2_SMALL_PAGE_ADDR_MASK 0xFFFFF
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#define ARM_MMU_ADDR_BELOW_PAGE_GRAN_MASK 0xFFF
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#define ARM_MMU_PTE_ID_INVALID 0x0
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#define ARM_MMU_PTE_ID_L2_PT 0x1
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#define ARM_MMU_PTE_ID_SECTION 0x2
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#define ARM_MMU_PTE_ID_LARGE_PAGE 0x1
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#define ARM_MMU_PTE_ID_SMALL_PAGE 0x2
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#define ARM_MMU_PERMS_AP2_DISABLE_WR 0x2
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#define ARM_MMU_PERMS_AP1_ENABLE_PL0 0x1
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#define ARM_MMU_TEX2_CACHEABLE_MEMORY 0x4
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#define ARM_MMU_TEX_CACHE_ATTRS_WB_WA 0x1
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#define ARM_MMU_TEX_CACHE_ATTRS_WT_nWA 0x2
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#define ARM_MMU_TEX_CACHE_ATTRS_WB_nWA 0x3
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#define ARM_MMU_C_CACHE_ATTRS_WB_WA 0
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#define ARM_MMU_B_CACHE_ATTRS_WB_WA 1
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#define ARM_MMU_C_CACHE_ATTRS_WT_nWA 1
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#define ARM_MMU_B_CACHE_ATTRS_WT_nWA 0
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#define ARM_MMU_C_CACHE_ATTRS_WB_nWA 1
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#define ARM_MMU_B_CACHE_ATTRS_WB_nWA 1
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/*
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* The following defines might vary if support for CPUs without
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* the multiprocessor extensions was to be implemented:
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*/
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#define ARM_MMU_TTBR_IRGN0_BIT_MP_EXT_ONLY BIT(6)
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#define ARM_MMU_TTBR_NOS_BIT BIT(5)
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#define ARM_MMU_TTBR_RGN_OUTER_NON_CACHEABLE 0x0
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#define ARM_MMU_TTBR_RGN_OUTER_WB_WA_CACHEABLE 0x1
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#define ARM_MMU_TTBR_RGN_OUTER_WT_CACHEABLE 0x2
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#define ARM_MMU_TTBR_RGN_OUTER_WB_nWA_CACHEABLE 0x3
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#define ARM_MMU_TTBR_RGN_SHIFT 3
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#define ARM_MMU_TTBR_SHAREABLE_BIT BIT(1)
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#define ARM_MMU_TTBR_IRGN1_BIT_MP_EXT_ONLY BIT(0)
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#define ARM_MMU_TTBR_CACHEABLE_BIT_NON_MP_ONLY BIT(0)
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/* <-- end MP-/non-MP-specific */
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#define ARM_MMU_DOMAIN_OS 0
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#define ARM_MMU_DOMAIN_DEVICE 1
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#define ARM_MMU_DACR_ALL_DOMAINS_CLIENT 0x55555555
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#define ARM_MMU_SCTLR_AFE_BIT BIT(29)
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#define ARM_MMU_SCTLR_TEX_REMAP_ENABLE_BIT BIT(28)
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#define ARM_MMU_SCTLR_HA_BIT BIT(17)
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#define ARM_MMU_SCTLR_ICACHE_ENABLE_BIT BIT(12)
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#define ARM_MMU_SCTLR_DCACHE_ENABLE_BIT BIT(2)
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#define ARM_MMU_SCTLR_CHK_ALIGN_ENABLE_BIT BIT(1)
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#define ARM_MMU_SCTLR_MMU_ENABLE_BIT BIT(0)
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#define ARM_MMU_L2_PT_INDEX(pt) ((uint32_t)pt - (uint32_t)l2_page_tables) /\
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sizeof(struct arm_mmu_l2_page_table);
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union arm_mmu_l1_page_table_entry {
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struct {
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uint32_t id : 2; /* [00] */
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uint32_t bufferable : 1;
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uint32_t cacheable : 1;
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uint32_t exec_never : 1;
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uint32_t domain : 4;
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uint32_t impl_def : 1;
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uint32_t acc_perms10 : 2;
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uint32_t tex : 3;
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uint32_t acc_perms2 : 1;
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uint32_t shared : 1;
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uint32_t not_global : 1;
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uint32_t zero : 1;
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uint32_t non_sec : 1;
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uint32_t base_address : 12; /* [31] */
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} l1_section_1m;
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struct {
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uint32_t id : 2; /* [00] */
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uint32_t zero0 : 1; /* PXN if avail. */
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uint32_t non_sec : 1;
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uint32_t zero1 : 1;
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uint32_t domain : 4;
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uint32_t impl_def : 1;
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uint32_t l2_page_table_address : 22; /* [31] */
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} l2_page_table_ref;
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struct {
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uint32_t id : 2; /* [00] */
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uint32_t reserved : 30; /* [31] */
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} undefined;
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uint32_t word;
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};
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struct arm_mmu_l1_page_table {
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union arm_mmu_l1_page_table_entry entries[ARM_MMU_PT_L1_NUM_ENTRIES];
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};
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union arm_mmu_l2_page_table_entry {
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struct {
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uint32_t id : 2; /* [00] */
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uint32_t bufferable : 1;
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uint32_t cacheable : 1;
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uint32_t acc_perms10 : 2;
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uint32_t tex : 3;
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uint32_t acc_perms2 : 1;
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uint32_t shared : 1;
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uint32_t not_global : 1;
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uint32_t pa_base : 20; /* [31] */
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} l2_page_4k;
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struct {
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uint32_t id : 2; /* [00] */
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uint32_t bufferable : 1;
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uint32_t cacheable : 1;
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uint32_t acc_perms10 : 2;
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uint32_t zero : 3;
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uint32_t acc_perms2 : 1;
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uint32_t shared : 1;
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uint32_t not_global : 1;
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uint32_t tex : 3;
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uint32_t exec_never : 1;
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uint32_t pa_base : 16; /* [31] */
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} l2_page_64k;
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struct {
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uint32_t id : 2; /* [00] */
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uint32_t reserved : 30; /* [31] */
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} undefined;
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uint32_t word;
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};
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struct arm_mmu_l2_page_table {
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union arm_mmu_l2_page_table_entry entries[ARM_MMU_PT_L2_NUM_ENTRIES];
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};
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/*
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* Data structure for L2 table usage tracking, contains a
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* L1 index reference if the respective L2 table is in use.
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*/
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struct arm_mmu_l2_page_table_status {
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uint32_t l1_index : 12;
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uint32_t entries : 9;
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uint32_t reserved : 11;
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};
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/*
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* Data structure used to describe memory areas defined by the
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* current Zephyr image, for which an identity mapping (pa = va)
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* will be set up. Those memory areas are processed during the
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* MMU initialization.
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*/
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struct arm_mmu_flat_range {
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const char *name;
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uint32_t start;
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uint32_t end;
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uint32_t attrs;
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};
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/*
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* Data structure containing the memory attributes and permissions
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* data derived from a memory region's attr flags word in the format
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* required for setting up the corresponding PTEs.
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*/
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struct arm_mmu_perms_attrs {
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uint32_t acc_perms : 2;
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uint32_t bufferable : 1;
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uint32_t cacheable : 1;
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uint32_t not_global : 1;
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uint32_t non_sec : 1;
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uint32_t shared : 1;
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uint32_t tex : 3;
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uint32_t exec_never : 1;
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uint32_t id_mask : 2;
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uint32_t domain : 4;
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uint32_t reserved : 15;
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};
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#endif /* ZEPHYR_ARCH_AARCH32_ARM_MMU_PRIV_H_ */
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