Commit graph

360 commits

Author SHA1 Message Date
Andy Ross
e62e92fa2b arch: Remove FPU_SHARING dependence on MULTITHREADING
This was just a pedantic setting.  I mean, of course it makes no sense
to have thread FPU management state features built when you aren't
including the scheduler in the build.

...unless you want to unit-test the context switch code without
tripping over itself on the way into the test code.  In fact lots of
unit testing of low level primitives can be done with
MULTITHREADING=n.

Remove the dependency.  It isn't actually doing anything useful.

Signed-off-by: Andy Ross <andyross@google.com>
2026-03-10 17:24:10 +01:00
Bjarki Arge Andreasen
e56e06020c arch: kconfig: ISR_TABLES_LOCAL_DECLARATION depend on IRQ vector table
ISR_TABLES_LOCAL_DECLARATION depends on GEN_IRQ_VECTOR_TABLE but
this is not enforced in Kconfig.

Building without the GEN_IRQ_VECTOR_TABLE and with LOCAL_DECLARATION
will produce the following misleading static assertion error:

  "CONFIG_IRQ_VECTOR_TABLE_JUMP_BY_{ADDRESS,CODE} not set"

As the LOCAL_DECLARATION macros expect GEN_IRQ_VECTOR_TABLE to be
enabled. LOCAL_DECLARATION also depends on GEN_ISR_TABLES but that
is a dependency of GEN_IRQ_VECTOR_TABLE already.

Signed-off-by: Bjarki Arge Andreasen <bjarki.andreasen@nordicsemi.no>
2026-03-10 15:11:51 +01:00
Pete Johanson
15ac638118 soc: adi: Don't enable built in barriers for MAX32 RV32 core
The MAX32 RV32 core does not implement the fence instruction used by the
RISC-V synchronization intrinsic, so don't enable the builtin barriers for
that target.

Signed-off-by: Pete Johanson <pete.johanson@analog.com>
2026-02-25 18:47:53 +01:00
Mirai SHINJO
78718321e9 arch: riscv: coredump: add per-thread dump support
Select ARCH_SUPPORTS_COREDUMP_THREADS (if !SMP) and
ARCH_SUPPORTS_COREDUMP_STACK_PTR for RISC-V, and implement
arch_coredump_stack_ptr_get().

This enables CONFIG_DEBUG_COREDUMP_MEMORY_DUMP_THREADS and
CONFIG_DEBUG_COREDUMP_THREAD_STACK_TOP.

For non-current threads, return thread->callee_saved.sp.

For the faulting current thread in stack-top mode, return the
exception-time SP from z_riscv_get_sp_before_exc() (cached during
arch_coredump_info_dump()) instead of thread->callee_saved.sp,
which reflects switch-time state.

Signed-off-by: Mirai SHINJO <oss@mshinjo.com>
2026-02-18 10:31:33 +00:00
Fin Maaß
0da1b7870e arch: riscv: require "riscv" compatible
Require the "riscv" compatible for
CONFIG_RISCV.

Signed-off-by: Fin Maaß <f.maass@vogl-electronic.com>
2026-01-26 14:15:18 +01:00
Daniel Leung
3e33978078 cache: deprecate CONFIG_DOUBLEMAP
Use CONFIG_CACHE_HAS_MIRRORED_MEMORY_REGIONS instead.
The new kconfig reflects more correctly on what is going on
in hardware. Also, this is not enabled by default if CPU
cache is not coherent. CPU cache can be incoherent and yet
there are no mirrored memory regions. Those relying on this
deprecated default behavior has their config adding
CONFIG_CACHE_HAS_MIRRORED_MEMORY_REGIONS separately.

Signed-off-by: Daniel Leung <daniel.leung@intel.com>
2025-12-09 09:25:33 +01:00
Daniel Leung
a8c1df6b80 cache: adds CONFIG_SOC_CACHE
This allows SoC to define their custom cache related functions
and are used by sys_cache_*() functions.

Signed-off-by: Daniel Leung <daniel.leung@intel.com>
2025-12-09 09:25:33 +01:00
Daniel Leung
169304813a cache: move arch_mem_coherent() into cache subsys
arch_mem_coherent() is cache related so it is better to move it
under cache subsys. It is renamed to sys_cache_is_mem_coherent()
to reflect this change.

The only user of arch_mem_coherent() is Xtensa. However, it is
not an architecture feature. That's why it is moved to the cache
subsys.

Signed-off-by: Daniel Leung <daniel.leung@intel.com>
2025-12-09 09:25:33 +01:00
Daniel Leung
301abd8630 xtensa: imply CONFIG_ARCH_HAS_RESERVED_PAGE_FRAMES if MMU
The Zephyr linker script usually puts something before
z_mapped_start (where .text is), for example, vecbase vectors.
So we need to reserve those space or else k_mem_map() would be
mapping those which may result in faults.

To avoid mapping there, CONFIG_ARCH_HAS_RESERVED_PAGE_FRAMES
needs to be used. Since it is common when MMU is enabled, we
should enable it by default using imply. All current Xtensa
MMU SoCs all have this selected anyway. Using 'imply' instead
of 'select' is to allow it to be disabled if so desired.

Signed-off-by: Daniel Leung <daniel.leung@intel.com>
2025-12-09 09:25:33 +01:00
Daniel Leung
48537aeb1f xtensa: CONFIG_ARCH_HAS_USERSPACE should be in arch layer
CONFIG_ARCH_HAS_USERSPACE should be in arch layer as MMU and MPU
support both in the arch layer.

Signed-off-by: Daniel Leung <daniel.leung@intel.com>
2025-12-09 09:25:33 +01:00
Carles Cufi
db0c34d836 c standard: Default to C17 as the minimum required C standard
C99 has been the minimum required C standard version for Zephyr since
its inception. After multiple attempts and discussions, a decision has
been made to upgrade to C17 going forward.
This commits replaces the default C standard from C99 to C17 in the
configuration and build system, and deprecates support for the older
standards.

Signed-off-by: Carles Cufi <carles.cufi@nordicsemi.no>
2025-11-20 09:04:46 -05:00
Daniel Leung
38d49efdac kernel: mem_domain: keep track of threads only if needed
Adds a new kconfig CONFIG_MEM_DOMAIN_HAS_THREAD_LIST so that
only the architectures requiring to keep track of threads in
memory domains will have the necessary list struct inside
the memory domain structs. Saves a few bytes for those arch
not needing this.

Also rename the struct fields to be most descriptive of what
they are.

Signed-off-by: Daniel Leung <daniel.leung@intel.com>
2025-10-21 22:54:44 +03:00
Flavio Ceolin
d1287edc1f arch: native: Fix undefined symbols
CONFIG_FLASH_SIZE and CONFIG_FLASH_BASE_ADDRESS symbols were not defined in
native_sim even though it has a flash controller and flash defined.

Signed-off-by: Flavio Ceolin <flavio@hubble.com>
2025-09-10 22:39:43 -04:00
Mark Holden
827a4f7387 coredump: xtensa: Add support for ARCH_SUPPORTS_COREDUMP_STACK_PTR
Select ARCH_SUPPORTS_COREDUMP_STACK_PTR on xtensa, and provide an
implementation for the arch_coredump_stack_ptr_get function.

Signed-off-by: Mark Holden <mholden@meta.com>
2025-09-09 14:53:00 +02:00
Fin Maaß
a584e36e27 arch: cache: set default of line size
set default of line size to the
value from the devicetree.

Signed-off-by: Fin Maaß <f.maass@vogl-electronic.com>
2025-09-08 15:53:36 -04:00
Fin Maaß
f64126f487 arch: Kconfig: use if to siplify
use if to simplyfy dependencys.

Signed-off-by: Fin Maaß <f.maass@vogl-electronic.com>
2025-09-08 15:53:36 -04:00
Anas Nashif
cf6db903e1 kernel: move xip into arch/common
Not really a kernel feature, more for architecture, which is reflected
in how XIP is enabled and tested. Move it to architecture code to keep
which much of the 'implementation' and usage is.

Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2025-09-08 15:51:07 -04:00
Ederson de Souza
016eaf2959 kernel: Add interface for hardware shadow stack usage
In order to allow kernel created threads (such as main and idle threads)
to make use of hardware shadow stack implementation, add an interface
for them.

This patch basically provides an infra that architectures need to
implement to provide hardware shadow stack.

Also, main and idle threads are updated to make use of this interface
(if hardware shadow stacks are enabled).

Signed-off-by: Ederson de Souza <ederson.desouza@intel.com>
2025-09-02 07:56:48 +02:00
Bill Waters
77a62d1b5b linker: noint memory region location
- There are linker file directives that must come at the
  start of the noinit region.  For example, the directive
  that allow that section to not exist in RAM before a
  certain address (. = MAX(ABSOLUTE(.), 0x34002000);).
- Before this update, those could only be added to the end
  of that region.  They will now have the option to be at the
  beginning or the end.

Signed-off-by: Bill Waters <bill.waters@infineon.com>
2025-08-12 09:55:12 +03:00
Martin Hoff
d5f67d04ee arch: split dynamic interrupt symbol
This commit introduces the SRAM_SW_ISR_TABLE option which is selected by
DYNAMIC_INTERRUPT. It allows splitting the DYNAMIC_INTERRUPT option into
two parts:

 - One for the relocation of the ISR vector table in RAM
 - One for the inclusion of functions needed to install ISRs dynamically

The goal is to later only select the relocation of the ISR vector table in
RAM and not all the associated functions from the dynamic interrupt
mechanism.

Signed-off-by: Martin Hoff <martin.hoff@silabs.com>
2025-07-30 17:37:43 -04:00
Peter Mitsis
cd351208d5 arch: xtensa: Refine HiFi sharing Kconfigs
Splits HiFi sharing into two different models.
 1. XTENSA_EAGER_HIFI_SHARING - unconditional save/restore
    of the HiFi registers when context switching
 2. XTENSA_LAZY_HIFI_SHARING - on demand save/restore of
    of the HiFi registers. If a thread does not use the
    HiFi registers, they are neither saved nor restored.

To maintain backwards compatibility, the eager model is the
default model when XTENSA_HIFI_SHARING is enabled.

Signed-off-by: Peter Mitsis <peter.mitsis@intel.com>
2025-07-20 12:25:17 -04:00
Fin Maaß
514258aa23 riscv: select ATOMIC_OPERATIONS based on RISCV_ISA_EXT_A
use RISCV_ISA_EXT_A to select ATOMIC_OPERATIONS_BUILTIN or
ATOMIC_OPERATIONS_C.

Signed-off-by: Fin Maaß <f.maass@vogl-electronic.com>
2025-06-30 15:17:47 -05:00
Tom Hughes
6f433a93ab arch: riscv: core: Add support for CONFIG_ISR_TABLES_LOCAL_DECLARATION
Adjust the linker scripts to use the same setup as ARM for
CONFIG_ISR_TABLES_LOCAL_DECLARATION.

Signed-off-by: Tom Hughes <tomhughes@chromium.org>
2025-06-10 08:47:51 +02:00
Al Semjonovs
452fe47765 arch: Add config for downstream toolchains to support local ISR tables
Add config for local toolchains to indicate support for local
declaration of ISR tables.

Signed-off-by: Al Semjonovs <asemjonovs@google.com>
2025-06-09 15:04:25 -07:00
Tom Hughes
60045b5ee0 arch: Add LLVM toolchain to ISR_TABLES_LOCAL_DECLARATION_SUPPORTED
The LLVM toolchain can also compile this code.

Signed-off-by: Tom Hughes <tomhughes@chromium.org>
2025-06-04 08:46:35 +02:00
Hake Huang
8e2c053cd1 linker: device_state : add alignment setting
the device_state need realocate when boot as second core.
as the relocation does not know the alignment, this could
be a case that the next data is mis-place after relocation.

fix this by add a alignment in device_state section.

still need revert aec0355380
reported in #86871

fixes: #82841

Signed-off-by: Hake Huang <hake.huang@oss.nxp.com>
2025-05-29 20:22:57 -04:00
Anas Nashif
5fe84d5b69 arch: nios2: remove arch
Remove architecture and dependencies.
Remove altera HAL supporting nios2

Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2025-05-15 20:01:05 -04:00
Damian Krolik
222e0fcd06 debug: coredump: support dumping stack top only
Add Kconfig option to dump only a portion of stack from the
current stack pointer to the stack end. This is enough to
let gdb reconstruct the stack trace and can significantly
reduce the dump size. This is crucial if the core dump needs
to be sent over radio.

Additionally, add another option to set the limit for the
dumped stack portion.

Signed-off-by: Damian Krolik <damian.krolik@nordicsemi.no>
2025-05-12 19:19:25 +02:00
Phi Tran
7ac89d33b1 scripts: west: flash: Add support for .mot file format
Add support for .mot file flash using west flash command
The RX build output .mot as binary file to flash into
board

Signed-off-by: Phi Tran <phi.tran.jg@bp.renesas.com>
Signed-off-by: Duy Nguyen <duy.nguyen.xa@renesas.com>
2025-05-02 09:18:16 +02:00
Duy Nguyen
fb7bdf0df4 arch: Initial support for RX architecture support
This commit add require code for supporting RX architecture
to Zephyr, it include:
- Add require config and CMakelists for RX arch
- Intialization startup code for RX
- Interrupt and exception handling
- Thread creation adn thread context switch
- irq offload using SW interrupt

Signed-off-by: Duy Nguyen <duy.nguyen.xa@renesas.com>
2025-05-02 09:18:16 +02:00
Keith Packard
2d64237f44 cmake: Enable undefined behavior sanitizer on all targets
GCC and Clang support the undefined behavior sanitizer in any
configuration, the only restriction is that if you want to get nice
messages printed, then you need the ubsan library routines which are only
present for posix architecture or when using picolibc.

This patch adds three new compiler properties:

 * sanitizer_undefined. Enables the undefined behavior sanitizer.
 * sanitizer_undefined_library. Calls ubsan library routines on fault.
 * sanitizer_undefined_trap. Invokes __builtin_trap() on fault.

Overhead for using the trapping sanitizer is fairly low and should be
considered for use in CI once all of the undefined behavior faults in
Zephyr are fixed.

Signed-off-by: Keith Packard <keithp@keithp.com>
2025-05-02 01:16:18 +02:00
Martin Hoff
a085cfcd99 arch: add dependencie for CONFIG_SRAM_VECTOR_TABLE
Move SRAM_VECTOR_TABLE symbol from general Kconfig to Arch Kconfig
because it depends on the architecture possibility to relocate the
vector table.

Signed-off-by: Martin Hoff <martin.hoff@silabs.com>
2025-04-25 11:03:54 +02:00
Peter Mitsis
4bc5498399 kconfig: Remove stale references to _Swap()
_Swap() is obsolete and has since been replaced with z_swap().

Signed-off-by: Peter Mitsis <peter.mitsis@intel.com>
2025-04-16 01:10:15 +02:00
Jamie McCrae
9f12f8afb2 infrastructure: Remove hwmv1 support
Removes support for the deprecated hardware model version 1

Signed-off-by: Jamie McCrae <jamie.mccrae@nordicsemi.no>
2025-03-13 16:53:07 +00:00
Jordan Yates
06d7fe8bed arch: update USERSPACE dependencies
These symbols only need to exist if `USERSPACE` is enabled, not just if
the architecture supports it.

Signed-off-by: Jordan Yates <jordan@embeint.com>
2025-03-07 20:25:23 +01:00
Carles Cufi
6160ff24ef arch: local ISR table declaration: Remove experimental label
The local ISR table generation was introduced in 13638a0351, and
included in Zephyr v3.6.0.

Signed-off-by: Carles Cufi <carles.cufi@nordicsemi.no>
2024-12-05 12:29:58 +01:00
Andy Ross
f7c10ac194 arch: Let CONFIG_IRQ_OFFLOAD_NESTED be overridable
This is currently selected by the arch, but some devices (in paticular
xtensa ones which have configurable interrupt setups) might not
actually be able to effect an irq_offload() from within an ISR even
though we have code for it.

Make this a default and not a select so that lower layers can override
the setting.

Signed-off-by: Andy Ross <andyross@google.com>
2024-11-28 20:51:50 +01:00
Yong Cong Sin
d26c712258 arch: add new interfaces to set/get the current thread of current CPU
Add the following arch-specific APIs:
- arch_curr_thread()
- arch_set_curr_thread()

which allow SMP architectures to implement a faster "get current
thread pointer" than the default provided by the kernel. The 'set'
function is required for the 'get' to work, more on that later.

When `CONFIG_ARCH_HAS_CUSTOM_CURRENT_IMPL` is selected, calls to
`_current` & `k_sched_current_thread_query()` will be redirected to
`arch_curr_thread()`, which ideally should translate into a single
instruction read, avoiding the current
"lock > read CPU > read current thread > unlock" path in SMP
architectures and thus greatly improves the read performance.

However, since the kernel relies on a copy of the "current thread"s on
every CPU for certain operations (i.e. to compare the priority of the
currently scheduled thread on another CPU to determine if IPI should be
sent), we can't eliminate the copy of "current thread" (`current`) from
the `struct _cpu` and therefore the kernel now has to invoke
`arch_set_curr_thread()` in addition to what it has been doing. This
means that it will take slightly longer (most likely one instruction
write) to change the current thread pointer on the current
CPU.

Signed-off-by: Yong Cong Sin <ycsin@meta.com>
Signed-off-by: Yong Cong Sin <yongcong.sin@gmail.com>
2024-11-23 20:12:24 -05:00
Daniel Leung
01f8e0fa2d demand_paging: eviction: add kconfig CONFIG_EVICTION_TRACKING
This adds a new kconfig for eviction algorithm which needs page
tracking. When enabled, k_mem_paging_eviction_add()/_remove()
and k_mem_paging_eviction_accessed() must be implemented.
If an algorithm does not do page tracking, there is no need to
implement these functions, and no need for the kernel MMU code
to call into empty functions. This should save a few function
calls and some CPU cycles.

Note that arm64 unconditionally calls those functions so
forces CONFIG_EVICTION_TRACKING to be enabled there.

Signed-off-by: Daniel Leung <daniel.leung@intel.com>
2024-11-18 13:16:44 -05:00
Nicolas Pitre
66853f4307 x86: add support for on-demand mappings
This makes x86 compatible with K_MEM_MAP_UNPAGED.

Signed-off-by: Nicolas Pitre <npitre@baylibre.com>
2024-09-23 18:10:38 -04:00
Daniel Leung
2c551554e2 riscv: support dumping privilege stack during coredump
Adds some bits to enable dumping privilege stack during
coredump.

Signed-off-by: Daniel Leung <daniel.leung@intel.com>
2024-09-21 11:29:39 +02:00
Daniel Leung
a3f4251ed5 x86: coredump: support dumping privilege stack
Adds the bits to support dumping privilege stack during
coredump.

Signed-off-by: Daniel Leung <daniel.leung@intel.com>
2024-09-21 11:29:39 +02:00
Daniel Leung
4f52860fe0 debug: coredump: dump privileged stack
This adds the bits to call into architecture code to dump
the privileged stack for user threads.

The weak implementation is simply there as a stub until
all architectures have implemented the associated function.

Signed-off-by: Daniel Leung <daniel.leung@intel.com>
2024-09-21 11:29:39 +02:00
Yong Cong Sin
b55f3c1c4f kernel: remove CONFIG_MP_NUM_CPUS
`CONFIG_MP_NUM_CPUS` has been deprecated for more than 2
releases, it's time to remove it.

Updated all usage of `CONFIG_MP_NUM_CPUS` to
`CONFIG_MP_MAX_NUM_CPUS`

Signed-off-by: Yong Cong Sin <ycsin@meta.com>
Signed-off-by: Yong Cong Sin <yongcong.sin@gmail.com>
2024-09-19 18:28:37 +01:00
Tavish Naruka
b1af1928f8 cmake: set big-endian flags to TOOLCHAIN_*_FLAGS
Set -big-endian to both compiler and linker flags if
CONFIG_BIG_ENDIAN is set.

Signed-off-by: Tavish Naruka <t-naruka@ispace-inc.com>
2024-09-19 03:30:14 -04:00
Nicolas Pitre
c99371e486 arm64: demand paging is supported
Test configs for UP and SMP are also included.

Signed-off-by: Nicolas Pitre <npitre@baylibre.com>
2024-09-11 20:18:51 -04:00
Magdalena Pastula
0237d375de arch: riscv: add an option for empty spurious interrupt handler
Add the possibility to disable fault handling in spurious
interrupt handler on RISCs and replacce it with an infinite loop.

Signed-off-by: Magdalena Pastula <magdalena.pastula@nordicsemi.no>
2024-09-02 12:35:57 -04:00
Marcio Ribeiro
cb583995b8 arch: riscv: imply XIP config pushed to SoC level
'imply XIP' pushed from arch/Kconfig/'config RISCV' to riscv SoCs Kconfig
files to allow riscv SoCs having XIP enabled (or not) at SoC level

Signed-off-by: Marcio Ribeiro <marcio.ribeiro@espressif.com>
2024-08-31 06:47:52 -04:00
Daniel Leung
0962114f2b riscv: implements arch_thread_priv_stack_space_get
This implements arch_thread_priv_stack_space_get() so this can
be used to figure out how much privileged stack space is used.

Signed-off-by: Daniel Leung <daniel.leung@intel.com>
2024-08-28 06:50:30 -04:00
Daniel Leung
55ee97c7d2 xtensa: implements arch_thread_priv_stack_space_get
This implements arch_thread_priv_stack_space_get() so this can
be used to figure out how much privileged stack space is used.

Signed-off-by: Daniel Leung <daniel.leung@intel.com>
2024-08-28 06:50:30 -04:00