Instead of using MCOX specific check with STM32MP1 devices,
the dedicated enable bit is defined in device tree.
This breaks compatibility with old DT overlays for
STM32MP13 devices.
The new overlay should now have 2 clocks, where the 1st one
is the enable bit, e.g. like:
clocks = <&rcc MCO1CFGR_REG BIT(12)>, <&rcc ...>;
Signed-off-by: Adam BERLINGER <adam.berlinger@st.com>
The change introduces clock-names into the MCO device tree.
This shouldn't break compatibility with existing DT overlays.
It clarifies the clock configuration for devices
with dedicated enable bit for MCO.
Signed-off-by: Adam BERLINGER <adam.berlinger@st.com>
nrf5340dk k_cycle_get_32() returns value for 32kHz RTC clock. It means
that can only be used to relatively slow signals. Increasing PWM period
100x to 16ms so that captured results return accepted deviation.
Signed-off-by: Krzysztof Chruściński <krzysztof.chruscinski@nordicsemi.no>
Adapt all Espressif SoC and driver code to the updated
hal_espressif module synced with IDF master branch.
Main changes:
- clock control: delegate peripheral clock gating to HAL
layer using new clock/reset APIs
- SPI/GDMA: adapt to restructured DMA HAL with new channel
allocation and configuration interfaces
- ethernet: add RMII clock configuration and PHY management
- GPIO: simplify using direct HAL function calls
- flash: adapt to updated SPI flash HAL interfaces
- linker scripts: update IRAM/DRAM mappings for new HAL
object files
- DTS: fix ESP32-S2 PSRAM dcache1 address to match actual
MMU mapping region (0x3f800000 DRAM1 instead of 0x3f500000
DPORT which lacks 8-bit access capability)
- west.yml: update hal_espressif revision
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
Add an opt-in Kconfig option to use the RP2350 untranslated XIP alias
for flash reads. This ensures the flash API can still access physical
partitions when Address Translation has remapped the primary window.
It otherwise introduces no changes for existing applications.
Signed-off-by: Raul Hernandez <raul.hernandez@spaceface.dev>
Prevent cppcheck-preprocessorErrorDirective failures by
passing includes to both autoconf.h and a generated header file
containing compiler-specific definitions to Cppcheck
Signed-off-by: Martin Lampacher <martin.lampacher@gmail.com>
Update completion scripts to use `west boards --all-targets` to obtain
the list of targets, instead of using shell black magic to perform
string parsing and modification. As a result, all shells get board
revision support.
Signed-off-by: Jordan Yates <jordan@embeint.com>
Add an option to `west boards` that automatically outputs all valid
board targets as a newline separated list without requiring any post
processing.
Signed-off-by: Jordan Yates <jordan@embeint.com>
Move the get_regs(dev) call after DEVICE_MMIO_MAP() to ensure the MMIO
region is mapped before retrieving the register base.
This fixes the potential invalid MMIO access.
Signed-off-by: Muhammad Waleed Badar <walid.badar@gmail.com>
Add missing dummy macro define HSUSBD_BUSINTEN_SOFIEN_Msk for when
CONFIG_UDC_ENABLE_SOF is enabled to pass compile for USBD
Fixes: #102173
Signed-off-by: Chun-Chieh Li <ccli8@nuvoton.com>
Add documentation about the ELE (EdgeLock Enclave) active timer
requirement for RT1180-based boards. This requirement is described
in RT1180 SRM section 3.11 and mandates that the ELE must be pinged
at least once every 24 hours to prevent system reset.
Signed-off-by: Lucien Zhao <lucien.zhao@nxp.com>
The RT1180 platform requires periodic communication with the EdgeLock
Enclave (ELE) to prevent system reset. According to RT1180 SRM section
3.11 "ELE active timer", the ELE must be pinged at least once every
24 hours.
This commit implements ELE ping functionality using Zephyr's software
timer API (k_timer). The timer is configured to ping the ELE every
23 hours (instead of 24) to account for potential clock inaccuracies.
Signed-off-by: Lucien Zhao <lucien.zhao@nxp.com>
If CONFIG_HTTP_SERVER_MAX_HEADER_LEN is increased from the default of
32, a compiler warning pops in the HTTP websocket code:
zephyr/subsys/net/lib/http/http_server_http1.c:
In function 'on_header_value':
zephyr/subsys/net/lib/http/http_server_http1.c:898:33:
warning: 'strncpy' output may be truncated copying between 0 and 32
bytes from a string of length 47 [-Wstringop-truncation]
898 | strncpy(ctx->ws_sec_key, ctx->header_buffer,
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
899 | MIN(sizeof(ctx->ws_sec_key), offset));
| ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
This comes from:
if (ctx->websocket_sec_key_next) {
#if defined(CONFIG_WEBSOCKET)
strncpy(ctx->ws_sec_key, ctx->header_buffer,
MIN(sizeof(ctx->ws_sec_key), offset));
#endif
If eg. header_buffer is 48 bytes and holds a string >= 32 bytes then
ws_sec_key can end up non-nul terminated. That can then lead to buffer
overflow in handle_http1_to_websocket_upgrade().
Add a check to make sure the header value fits in ws_sec_key, if not
reject the request with a HTTP 500. The websocket key is not expected to
be > 31 bytes.
Once the check is in place, it's safe to use memcpy() for the copy, and
then add the terminating nul manually.
Signed-off-by: Michael Ellerman <mpe@oss.tenstorrent.com>
Add support for PM policy device constraints to the MCUX LPADC driver.
This allows the driver to specify that certain power states should be
disabled when the device is active, which can help ensure proper operation
and reduce power consumption.
Signed-off-by: Zhaoxiang Jin <Zhaoxiang.Jin_1@nxp.com>
`THREAD_RUNTIME_STATS` is not a requirement for the thread analyzer to
operate, merely useful. Switch the control to `configdefault` to leave
it enabled by default, while allowing both applications to disable the
option with `CONFIG_THREAD_RUNTIME_STATS=n` and for alternate defaults
to be specified elsewhere.
Signed-off-by: Jordan Yates <jordan@embeint.com>
This might be just a cosmetic change, but caused me to study logs
a bit longer to understand.
When in the AWAIT_POWER_ON state, we do open an UART, but we
immediately attach the chat module into the UART, so we don't see the
log message "event bus opened".
Signed-off-by: Seppo Takalo <seppo.takalo@nordicsemi.no>
Add USB device next (usbd) feature support for the SAM V71
Xplained Ultra board. Add the revison B board to USB sample
integration platforms.
Signed-off-by: Gerson Fernando Budke <nandojve@gmail.com>
Add Atmel SAM USBHS driver for SAM E70/S70/V70/V71 family. The driver
was tested using CDC-ACM and testusb samples.
Fixes: #74663
Signed-off-by: Gerson Fernando Budke <nandojve@gmail.com>
Update the @param documentation for qspi_npcx_fiu_uma_block to match the
actual function signature, changing lock to lock_en.
Signed-off-by: Firas Sammoura <fsammoura@google.com>
Rename microchip,aes-g1 binding file to match compatible, fixes a:
dts/bindings/crypto/microchip,aes-g1-crypto.yaml: bad file name for
compatible 'microchip,aes-g1'; this should be named
'microchip,aes-g1.yaml' instead
error on unrelated PRs.
Signed-off-by: Fabio Baltieri <fabiobaltieri@google.com>
When we start uAP by specifying the network interface "-i" like this:
wifi ap enable … -i 1
(here: 1 is STA iface, 2 is uAP iface)
Currently, get_iface() uses interface index to choose the network
interface, but we do not check if the selected interface is correct
type.
So if the user specified interface is valid interface, we then verify
that it matches the given type. If there is no match, we return an
error and do not select a default type interface.
Signed-off-by: Li Long <li.long@nxp.com>
Reduces the amount of RAM available here, as MCUboot is set to use
30KiB of RAM which conflicts
Signed-off-by: Jamie McCrae <jamie.mccrae@nordicsemi.no>
Removes an invalid build configuration for RAM load which uses
shell and UART transports, because they conflict
Signed-off-by: Jamie McCrae <jamie.mccrae@nordicsemi.no>
Stop requesting west extension authors to "keep in sync" an unused .help
duplicate. Empty such duplicates from existing extensions. They cannot
be `None` yet because current west versions unfortunately require them.
Since the beginning of west extensions (2019 commit d3bb3cfd7a)
extension authors have been requested to provide not just a "help" field
in west-commands.yml, but also a duplicate in their WestCommmand
constructor than they should carefully "keep in sync".
While doing some unrelated extension work, I discovered by chance
that this duplicate has never been used. See detailed analysis in
https://github.com/zephyrproject-rtos/west/issues/927, shorter analysis
in https://github.com/zephyrproject-rtos/west/pull/933 and smoking gun
in the "TODO" comment added by west commit
0d39b6b77a
Signed-off-by: Marc Herbert <Marc.Herbert@gmail.com>
The simulated flash driver incorrectly applied the no_explicit_erase
capability. It was overriding Kconfig settings with a missing Devicetree
property, which caused RAM-like configurations to wrongly report needing
explicit erases before writes.
This commit fixes the initialization macro to correctly check the DT
instance property no-explicit-erase, while properly falling back to the
global CONFIG_FLASH_SIMULATOR_EXPLICIT_ERASE Kconfig.
A new runtime test is also added to properly verify this capability.
Fixes#100352Fixes#100400
Signed-off-by: Seyoung Jeong <seyoungjeong@gmail.com>
On macOS, calling socket.connect() may fail with
OSError(22, 'Invalid argument') if it occurs at a certain point after
JLinkGDBServer has started. This leaves the socket in an unrecoverable
state, meaning that all subsequent connection attempts using the same
socket fail with the same error.
The fix is to close the socket on known errors, wait, create a new
socket and try to connect again.
Signed-off-by: Ilia Kharin <akscram@gmail.com>
The Microchip MEC172x board DTS files enable I2C controllers.
We updated these nodes based on the changes to the V2 I2C
driver device tree. GIRQ and PCR properties are being
standardized as encoded integers. The I2C V2 driver now requires
phandes to the GPIO's for SCL and SDA pins for reading pin
states.
Signed-off-by: Scott Worley <scott.worley@microchip.com>
We update MEC172x and MEC174x/5x/165x device tree I2C hardware
nodes with properties used by the updated I2C V2 driver. GIRQs
are an array of integers where each integer encodes the GIRQ
number and bit position of each interrupt source. The PCR property
is a single integer encoding the PCR register index and bit position.
Signed-off-by: Scott Worley <scott.worley@microchip.com>
We will standardize how the I2C driver supporting MEC172x/4x/5x
and onwards gets the states of the SCL and SDA lines. For MEC172x we
use the Zephyr GPIO driver to get the pin states. For MEC174x/5x and
future parts based on v3.8 I2C hardware we can use a new feature
of the bit-bang control register allowing live reading of the pin
states without switching the internal MUX. The SoC common code
for MEC172x to read GPIO's using direct register access is
removed by this commit.
Signed-off-by: Scott Worley <scott.worley@microchip.com>
We modified the Microchip XEC/MEC version 2 I2C byte mode driver
to work on v3.8 I2C hardware in MEC174x/5x/165x SoCs. The changes
are as follows:
1. Add a local header file containing register and bit field definitions
2. Use Zephyr inline register access functions (sys_read/write)
instead of CMSIS register structures.
3. Change DT bindings to require GPIO references for the SCL and SDA
pins. MEC172x will use GPIO driver to get line states. MEC174x/5x
have v3.8 I2C hardware with read-only live values of SCL/SDA pin
states in the bit-bang control register. The MEC172x SoC code to
read I2C GPIO's is no longer needed and is removed in a later
commit in this series.
4. Use WAIT_FOR macro in place of custom spin loops.
5. SonarQube code check recommendations except WAIT_FOR macro which is
based on a GNU compiler extension.
Signed-off-by: Scott Worley <scott.worley@microchip.com>
