These bindings' filenames don't match their compatibles, but the fixes
weren't automated as there were multiple possible outcomes for these.
I looked around and fixed them up by hand.
Signed-off-by: Martí Bolívar <marti.bolivar@oss.qualcomm.com>
Clean up various bindings whose names do not match our naming policy.
These are all unambiguous cases I found and fixed with a quick script.
As a reminder, the policy in bindings-upstream.rst is:
Bindings which match a compatible must have file names based on
the compatible.
- For example, a binding for compatible ``vnd,foo`` must be named
``vnd,foo.yaml``.
- If the binding is bus-specific, you can append the bus to the
file name; for example, if the binding YAML has ``on-bus: bar``,
you may name the file ``vnd,foo-bar.yaml``.
Signed-off-by: Martí Bolívar <marti.bolivar@oss.qualcomm.com>
This fixes a regression introduced with commit fc2b1b2f3e.
This ensures that when the UAOL driver is disabled, the DAI UAOL
driver is also disabled.
Signed-off-by: Serhiy Katsyuba <serhiy.katsyuba@intel.com>
Adjust the backup SRAM initialization to PRE_KERNEL_1 to ensure it's
initialized before any retained_mem instances placed into that area.
Signed-off-by: Pete Johanson <pete.johanson@analog.com>
Add board support for the Alif Ensemble E1C Development Kit
featuring the Ensemble E1C SoC.
The Ensemble E1C SoC contains a single Cortex-M55 CPU cluster:
RTSS-HE (High Efficiency, up to 160 MHz). Following the hardware
model, the CPU cluster is defined as a board target:
- ensemble_e1c_dk/ae1c1f4051920ph0/rtss_he
Initial support includes UART for console output.
Link: https://alifsemi.com/support/kits/ensemble-e1cdevkit/
Signed-off-by: Silesh C V <silesh@alifsemi.com>
Add Ensemble E1C series specific pin multiplexing definitions.
The E1C series has different hardware peripheral routing compared
to the existing E4/E6/E8 series. So separate pin definitions are
needed. But as the pinctrl register layout and control
logic are identical across all Ensemble series, the same driver
and encoding scheme can be reused.
Signed-off-by: Silesh C V <silesh@alifsemi.com>
Add device tree include file for the Alif Ensemble E1C SoC
variant AE1C1F4051920PH0.
The file builds upon the common peripheral definitions from
ensemble_common.dtsi and ensemble_rtss_he.dtsi and defines the
SoC specific clock frequencies, TCM configurations and MRAM
configuration.
Signed-off-by: Silesh C V <silesh@alifsemi.com>
Add support for the Ensemble E1C series and the AE1C1F4051920PH0
SoC within this series. The E1C (E1 Compact) series contains a
single Cortex-M55 core configured as RTSS-HE (High Efficiency
Real Time Subsystem) with a maximum frequency of 160 MHz.
The E1C series uses SOC_FAMILY_ENSEMBLE_RTSS helper symbol
introduced earlier to share the CPU architecture configuration
with the E4, E6, and E8 series.
Link: https://alifsemi.com/ensemble-e1c-series/
Signed-off-by: Silesh C V <silesh@alifsemi.com>
Don't allow the LPTIM system clock driver to be enabled if the required
nodelabel `stm32_lp_tick_source` does not exist. This prevents incorrect
usage which could result in non-trivial build failures.
Signed-off-by: Mathieu Choplain <mathieu.choplain-ext@st.com>
The `stm32_lp_tick_source` nodelabel must be placed on a low-power timer to
use it as system clock timer. This was not done by this board so the
Kconfig was unable to determine which clock source was used, and ultimately
resulting in a build error because option `STM32_LPTIM_TIMEBASE` had no
value.
Fix by adding the missing nodelabel.
Signed-off-by: Mathieu Choplain <mathieu.choplain-ext@st.com>
Main changes since v3.0
* libUtilv1: dump_files: Fix in file access macros
Note: Like before, bsim remains fully backwards compatible
Signed-off-by: Alberto Escolar Piedras <alberto.escolar.piedras@nordicsemi.no>
It's been observed in the CI that DHCPv4 server tests fail occasionally
due to timeouts, therefore increase certain timeouts/delays to increase
tests stability under heavy load. At least locally I was no longer able
to reproduce the failures.
Signed-off-by: Robert Lubos <robert.lubos@nordicsemi.no>
Add a test that verifies periodic compare event generation
using the GRTC interval feature.
Signed-off-by: Adam Kondraciuk <adam.kondraciuk@nordicsemi.no>
Add support for hardware-generated periodic compare events using
the GRTC interval feature. Once configured, the hardware generates
compare events at a fixed interval without CPU intervention.
The feature is available only on channels defined as
"extended-channels" in the devicetree.
Signed-off-by: Adam Kondraciuk <adam.kondraciuk@nordicsemi.no>
Update the HW models module to:
2b09581c7654f4dfd38681270350c9ae6b0438a2
Including the following:
2b09581 Refactor target specific code and definitions
da1f4e3 hal: nrfx_common replacement: Minor refactor
c2ca4ec RADIO: Refactor getting frequency and Tx power
Signed-off-by: Alberto Escolar Piedras <alberto.escolar.piedras@nordicsemi.no>
Some boards enable both IWDG & WWDG at board level which only one
is aliased as watchdog0. In such case only keep the one aliased
and keep the 2nd one disabled.
Signed-off-by: Alain Volmat <alain.volmat@foss.st.com>
The wdt_basic_api test program first check for the watchdog0 alias
prior to checking for available compatible. Lots of STM32 board
already define the watchdog0 alias at board level hence in such
case the watchdog set at board level will be picked up and not
the one necessarily intended in the test.
Add setting of the watchdog0 alias as part of the stm32 overlays.
Signed-off-by: Alain Volmat <alain.volmat@foss.st.com>
The STM32N6 embeds two kind of watchdogs for which this
commit adds the nodes.
- System window watchdog (WWDG)
- Independent watchdog (IWDG)
Signed-off-by: Alain Volmat <alain.volmat@foss.st.com>
EXPECTED_SIZE must be a multiple of the write block size. The same
applies to CONFIG_FLASH_FILL_BUFFER_SIZE. Ensure EXPECTED_SIZE is
at least as large as the flash fill buffer, which is already adjusted
via config overlays for boards/chips with a particularly large write
block size.
Signed-off-by: Tim Pambor <tim.pambor@codewrights.de>
is_fatal_error is used to determine whether an exception is
a fatal one. In the default switch case for exception handling,
is_fatal_error needs to be set true. However, setting this
variable was done after stack bound check. So if stack bound
check fails, is_fatal_error is never set. So set the variable
earlier before the stack bound check.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
Fix buffer pool allocation size for BR/EDR L2CAP non-basic modes by
using the appropriate macro that accounts for SDU segmentation
overhead.
The previous implementation used BT_L2CAP_BUF_SIZE() which is designed
for basic mode and does not account for the additional overhead
required when segmenting SDUs in retransmission or flow control modes
(I-frame control field, FCS, and SDU length field).
- Replace BT_L2CAP_BUF_SIZE() with BT_L2CAP_RT_FC_MAX_SDU_BUF_SIZE()
- Ensures sufficient buffer space for segmented I-frames
- Aligns buffer allocation with recent MPS and MTU calculation fixes
This prevents potential buffer overruns when transmitting segmented
SDUs in non-basic modes.
Signed-off-by: Lyle Zhu <lyle.zhu@nxp.com>
Simplify the PDU length calculation in get_pdu_len() by using the
configured MPS value directly without manual adjustments for overhead.
The previous implementation attempted to manually calculate available
payload space by subtracting header/tail sizes and then adding back
the SDU length field size, which was unnecessarily complex and
error-prone.
- Remove manual calculation of actual_mps with header/tail overhead
- Use br_chan->tx.mps directly as the MPS limit
- Remove special handling for start segments (SDU length field
adjustment)
- Simplify logic: return pdu_len if within MPS, otherwise return MPS
The MPS value already represents the maximum PDU size that can be
transmitted, so no additional adjustments are needed. This aligns with
the recent fixes to MPS validation and MTU calculation.
Signed-off-by: Lyle Zhu <lyle.zhu@nxp.com>
Fix incorrect MPS validation for segmented I-frames by extracting the
SDU length field before checking payload size against MPS.
When an I-frame has SAR (Segmentation and Reassembly) set to START,
it contains a 2-byte SDU length field that precedes the actual payload.
The previous implementation validated buf->len against MPS before
removing this header, causing false positives when the SDU length field
pushed the total size over MPS.
- Extract SAR field from control header for all L2CAP modes
- Initialize SAR to UNSEG by default
- Pull SDU length (2 bytes) when SAR indicates START segment
- Perform MPS validation after SDU length extraction
- Move net_buf_simple_save/restore to encompass SDU length handling
This ensures MPS validation checks only the actual payload size,
preventing spurious disconnections for legitimate segmented transfers.
Signed-off-by: Lyle Zhu <lyle.zhu@nxp.com>
Fix incorrect RX MTU calculation when retransmission/flow control modes
are enabled. The previous implementation did not account for I-frame
overhead (control field and FCS), which could cause MTU to exceed the
maximum I-frame payload.
- Add l2cap_br_get_rx_mtu() helper to calculate proper RX MTU
- Discount extended control field size (4 bytes) when enhanced
retransmission or streaming mode is enabled
- Discount standard control field size (2 bytes) for basic mode
- Always discount FCS size (2 bytes) as it may be required by peer
- Add assertion to validate MTU meets minimum requirements
- Update l2cap_br_check_chan_config() to use new MTU calculation
This ensures the negotiated MTU fits within the I-frame payload limits
and prevents buffer overruns in non-basic L2CAP modes.
Signed-off-by: Lyle Zhu <lyle.zhu@nxp.com>
Add board overlay and configuration files to support dma tests
on CY8CPROTO-041TP board.
Signed-off-by: Dharun krithik k <dharunkrithik@aerlync.com>
Signed-off-by: Sayooj K Karun <sayooj@aerlync.com>
Add a new DMA driver for the Infineon DMAC (Direct Memory Access
Controller) specifically for PSoC4 Series.
Signed-off-by: Dharun krithik k <dharunkrithik@aerlync.com>
Signed-off-by: Sayooj K Karun <sayooj@aerlync.com>
Add DMA controller node to PSoC 4100TP device tree and introduce
the corresponding binding file `infineon,dmac.yaml`.
Signed-off-by: Dharun krithik k <dharunkrithik@aerlync.com>
Signed-off-by: Sayooj K Karun <sayooj@aerlync.com>
Add a section about the new `st,stm32-nvm-otp` compatible and corresponding
driver to the 4.4 release notes.
Signed-off-by: Mathieu Choplain <mathieu.choplain-ext@st.com>
Extends the adc_dt sample with an option to use with the
eval_cn0391_ardz shield, which provides an adi ad7124-8 multichannel
adc.
Signed-off-by: Maureen Helm <maureen.helm@analog.com>
Adds a new shield definition for the Analog Devices EVAL-CN0391-ARDZ
thermocouple shield. This shield provides support for an ADI AD7124-8
multichannel, 24-bit, sigma-delta ADC over an Arduino SPI connector.
Signed-off-by: Maureen Helm <maureen.helm@analog.com>
Signed-off-by: Raluca Bozdog <raluca.bozdog@analog.com>
Modifies the adc_dt sample to increase the sample buffer size to support
ADCs with more than 16 bits of resolution, such as ad7124.
Signed-off-by: Maureen Helm <maureen.helm@analog.com>
TISCI_GET_CLOCK_DETAILS_BY_INST takes the instance number of the DT node,
this is supposed to be denoted by `inst`. However, due to a typo it is
currently DT_DRV_INST which makes no sense since that is a separate macro
of its own. Hence, fix this typo.
Signed-off-by: Amneesh Singh <amneesh@ti.com>
Add a new field to the `sntp_time` struct which is an estimate of the
delay between the SNTP server sending the response and the SNTP client
(the application) receiving it. This information can then be used by
the caller to correct for the systemic bias introduced by non-zero
network latencies.
Includes internal variable naming to make it clearer which timestamps
are which.
Signed-off-by: Jordan Yates <jordan@embeint.com>
Add shield definition for the MikroElektronika Flash 6 Click shield,
an mikroBUS compatible evaluation module for the Winbond W25Q128JV
(128M-bit) SPI Serial NOR Flash chip.
Tested with the command mentioned on the index.rst page.
Signed-off-by: Stephan Linz <linz@li-pro.net>
