Add the support of the stm32mp13 ethernet:
- Adapt to HAL API
- Add support of a memory region in DT for descriptor and buffers
- Add support of PHY with/without crystal 50MHz
Signed-off-by: Arnaud Pouliquen <arnaud.pouliquen@foss.st.com>
Signed-off-by: Arif Balik <arifbalik@outlook.com>
The typedef ETH_TxPacketConfigTypeDef is used consistently in the driver.
However, some instances of ETH_TxPacketConfig have not yet been replaced.
On the STM32MP13 series, the ETH_TxPacketConfig typedef is no longer
defined. This cleanup ensures compatibility and consistency.
Signed-off-by: Arnaud Pouliquen <arnaud.pouliquen@foss.st.com>
Add the Ethernet 0 MAC and MDIO nodes in the device tree.
Signed-off-by: Arnaud Pouliquen <arnaud.pouliquen@foss.st.com>
Signed-off-by: Arif Balik <arifbalik@outlook.com>
Enable dynamic configuration of region mapping with a 1:1
virtual-to-physical address mapping.
This configuration is aligned with the static declaration of the
MMU table using MMU_REGION_FLAT_ENTRY macro.
Signed-off-by: Arnaud Pouliquen <arnaud.pouliquen@foss.st.com>
The GPIO_MCP230XX config currently depends on the I2C config. This means
that the board/SoC must enable the I2C config to support MCP23xxx devices.
Inverting this dependency allows declaring GPIO_MCP230XX directly in the
board/SoC defconfig without explicitly enabling I2C.
Signed-off-by: Arnaud Pouliquen <arnaud.pouliquen@foss.st.com>
Suggested-by Fin Maaß <f.maass@vogl-electronic.com>
Add basic support of the LAN8742 RMII phy. The driver is inspired
from the phy_mii generic driver, with the support of a GPIO reset.
Signed-off-by: Arnaud Pouliquen <arnaud.pouliquen@foss.st.com>
Introduce stm32mp13 bindings to support the ethernet peripherals.
The "memory-regions" property is used to reference non cacheable memory
for the ETH DMA.
The "st,ext-phyclk" property aligned Linux binding is used to specify
the PHY clock for RMII.
Signed-off-by: Arnaud Pouliquen <arnaud.pouliquen@foss.st.com>
- MSPM0L110x series SOC contain 2 UARTS. So add UART1.
- While all MSPM0L series SOC contain at least 2 UARTs, the address for
UART1 seems to be different in L222x and L122x (0x4010A000).
Signed-off-by: Ayush Singh <ayush@beagleboard.org>
Release the PM constraint at the end of the context in which it was
requested (`transceive`), instead of in a semi-related function
(`finalize_spi_transaction`) which is also called by other API functions
(`spi_release`). Asynchronous usage is released in the transaction
complete callback.
Signed-off-by: Jordan Yates <jordan@embeint.com>
This commit adds the implementation for the display_set_orientation API
to the ST7796S display driver.
Currently, the driver lacks support for changing the display orientation
at runtime. This change implements the API to allow for hardware-based
rotation using the MADCTL register.
The implementation was tested on an `rd_rw612_bga` board with a 320x480
display using the ST7796S controller. The API now correctly handles
rotations to 0, 90, 180, and 270 degrees by configuring the MY, MX, and
MV bits of the MADCTL register.
Signed-off-by: Nilesh Vyas <nileshvyas1112@gmail.com>
Users can choose blackmagicprobe to flash or debug the device,
without needing to set up ST’s customized OpenOCD.
Signed-off-by: MA Junyi <mjysci@live.com>
Add test support for sdhc driver on Renesas ek_ra8m1 and
ek_ra8p1 board:
- tests/drivers/disk/disk_access
Signed-off-by: Khoa Tran <khoa.tran.yj@bp.renesas.com>
Add sample support for sdhc driver on Renesas ek_ra8m1 and
ek_ra8p1 board:
- samples/subsys/fs/fs_sample
Signed-off-by: Khoa Tran <khoa.tran.yj@bp.renesas.com>
Update supported spi and sdhc tag for integration_platforms for
spi and disk test: ek_ra8m1, ek_ra8p1 cm85
Signed-off-by: Khoa Nguyen <khoa.nguyen.xh@renesas.com>
Add test support using SDMMC card on Renesas RA boards
Add Renesas RA board support for these tests:
- tests/drivers/disk/disk_access
Signed-off-by: Khoa Tran <khoa.tran.yj@bp.renesas.com>
Add test support using SDMMC card on Renesas RA boards
Add Renesas RA board support for these tests:
- tests/drivers/sdhc
Signed-off-by: Khoa Tran <khoa.tran.yj@bp.renesas.com>
driver using SDMMC card on Renesas RA boards
Add Renesas RA board support for these samples:
- samples/subsys/fs/fs_sample
Signed-off-by: Khoa Tran <khoa.tran.yj@bp.renesas.com>
Add Renesas RA board support for these tests:
- tests/drivers/spi/spi_loopback
- tests/drivers/spi/spi_controller_peripheral
Signed-off-by: Khoa Tran <khoa.tran.yj@bp.renesas.com>
for Renesas RA family
Add SPI device node to support SCI B SPI driver on Renesas RA SoCs:
- ra8x1.dtsi
- ra8x2.dtsi
Signed-off-by: Khoa Tran <khoa.tran.yj@bp.renesas.com>
When SPI spec is reconfigured, avoid reallocating another sm and properly
free the loaded sm programs before attempting to load new programs.
Fix#94416.
Signed-off-by: Terry Geng <terry@terriex.com>
TI MSPM0 has a TRNG module to generate truly random bits. Add a support
for TI MSPM0 TRNG module.
Signed-off-by: Sanjay Vallimanalan <sanjay@linumiz.com>
Enabled intel LPSS DMA interface using dw common to support
usage of internal DMA in LPSS SPI to transfer and
receive data.
Signed-off-by: Bindu S <bindu.s@intel.com>
There's a dual CAN interfce (J17) on sama7g54-ek board.
pin 1~5 siginal: CAN0_H, CAN0_L, GND, CAN1_H, CAN1_L.
The two CAN transceivers are controlled by PIOC15 and PIOC16 GPIOs.
Add CAN to the support list.
Signed-off-by: Tony Han <tony.han@microchip.com>
Update the driver (supporting samx7x SOCs) to support sama7g5 MCAN.
Differences lists bellow:
| samx7x MCAN | sama7g5 MCAN |
----------|---------------------------------|----------------------------|
CAN core | the same | the same |
clock | peripheral clock with a divider | generic & peripheral clock |
Msg RAM | address configured by CCFG_CAN0 | in SRAM, configured by SFR |
Signed-off-by: Tony Han <tony.han@microchip.com>
When the MCAN is activated in the DT, configure it's register region
with strong ordered, read and write access.
As CANx accesses the lower or upper 64K SRAM is selected by bits in
register 'SFR_CAN_SRAM_SEL', also configure SRAM and SFR region with
strong ordered, read and write access.
Signed-off-by: Tony Han <tony.han@microchip.com>
Support for the Silabs EFM32TG-STK3300 Starter Kit.
Board features:
* EFM32TG840F32 MCU with 32 kB flash and 4 kB RAM
* Advanced Energy Monitoring
* Real-time, accurate energy and power profiling
* Light, LC and touch sensors
* 8 x 20 LCD
* SEGGER J-Link debugger
Signed-off-by: Lukas Woodtli <woodtli.lukas@gmail.com>
* ARM Cortex-M3 processor
* Up to 32 kB Flash and 4 kB RAM memory
* Energy efficient and autonomous peripherals
* Ultra low power Energy Modes
* Fast wake-up
Signed-off-by: Lukas Woodtli <woodtli.lukas@gmail.com>
'GMAC_QUEUE_NUM' is a value of 'num-queues' for the first GMAC
instance getting from the device tree. It is used directly or
indirectly (by GMAC_PRIORITY_QUEUE_NUM) for defining and
initializing 'struct eth_sam_dev_data' with a value from Kconfig
(GMAC_ACTIVE_PRIORITY_QUEUE_NUM).
As there will be a big change for applying the corresponding
num-queues for each GMAC 'struct eth_sam_dev_data', here just
keep it as is. Adding the BUITD_ASSERT to make sure the array
queue_list[] is large enough for all GMAC instances.
Signed-off-by: Tony Han <tony.han@microchip.com>
Add variable 'random_mac_addr' for 'zephyr,random-mac-address' from
device tree. Update generate_mac() to get random MAC address for each
GAMC interface with the 'zephyr,random-mac-address' property.
Signed-off-by: Tony Han <tony.han@microchip.com>
Deprecate the 'ETH_SAM_GMAC_MAC_I2C_EEPROM' for the 'mac-eeprom' option,
Limite it to be used when there's only one activated GMAC instance.
Signed-off-by: Tony Han <tony.han@microchip.com>
As jumbo frame size is not supported by the networking subsystem, only
max_frame_size 1518 and 1536 can be used. The Frame size 1536 would
allow for packets with a vlan tag, so enable GMAC_NCFGR_MAXFS when
NET_VLAN is configured.
Signed-off-by: Tony Han <tony.han@microchip.com>
To allow every interface be initialized properly when there are more than
one instance, remove the static variable "init_done" which is used to make
the initialize procedure only be done once.
Signed-off-by: Tony Han <tony.han@microchip.com>
Add variable "ref_clk_source" to get and set the source for the GMAC
reference clock from DT for different GMAC instances.
Signed-off-by: Tony Han <tony.han@microchip.com>
Add variable "phy_conn_type" to get and use the phy_connection_type from
DT for different GMAC instances.
Update the judgement on phy_connection_type for multi instances support.
Signed-off-by: Tony Han <tony.han@microchip.com>
Change the driver from support 1 instance to support multi instances.
Changes includes:
- irq_config()
- config & data definitions
- ETH_NET_DEVICE_DT_INST_DEFINE
- PTP content / init / DEVICE_DEFINE
Limitations:
- generate_mac() to be updated for supporting multi instances.
- the configurations in Kconfig.sam_gmac are used for all instances.
Signed-off-by: Tony Han <tony.han@microchip.com>
Changes includes:
- add the variable for num_queues to eth_sam_dev_cfg
- update LOG with dev->name to distinguish different instances
Signed-off-by: Tony Han <tony.han@microchip.com>
The lists optimized includes:
- RX descriptors list
- TX descriptors list
- RX buffer accounting list
- TX buffer accounting list
- TX frames accounting list
Signed-off-by: Tony Han <tony.han@microchip.com>
The LoRaWAN subsystem does not require 2KiB of system workqueue,
testing on nrf54l15 flpr (RISCV) CPU (with custom cryptography code)
shows it uses about 700 bytes of the system workqueue, therefore it
is assumed that the real requirement for 2KiB is the software
cryptography features, not the LoRaWAN stack itself, and the
cryptography parts of LoRaWAN can be replaced with alternatives
that do not need this high of a memory requirement, so the
requirement has been moved to the specific Kconfig for software
cryptography instead
Signed-off-by: Jamie McCrae <spam@helper3000.net>
ARMv8-M and newer ARC MPUs use base/limit addressing with 32-byte
granularity and do not require power-of-two sizing. Only ARMv7-M
and older ARC MPUs have this restriction.
Check CONFIG_MPU_REQUIRES_POWER_OF_TWO_ALIGNMENT (set for ARMv7-M,
older ARC) instead of CONFIG_ARM_MPU to avoid wasting memory on
ARMv8-M systems.
Signed-off-by: Ibrahim Abdalkader <i.abdalkader@gmail.com>
This moves the switching stress test into its own group simply
to signify that there is a group for stress testing. And also
rename torture to stress.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
