Add sai3_2 and edma4_2 dts node for use with i2s_mcux_sai driver.
Signed-off-by: Yanan Yang <yanan.yang@nxp.com>
Fix indent format issue.
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Rework the driver to support i.MX9 platforms.
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Signed-off-by: Yanan Yang <yanan.yang@nxp.com>
Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.com>
Change to use device model MMIO mapping APIs.
Signed-off-by: Yanan Yang <yanan.yang@nxp.com>
Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.com>
Fix CI failures: Clean unused code
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
The burst length should be initialized with 'word_size_bits'.
Signed-off-by: Yanan Yang <yanan.yang@nxp.com>
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
add SAI clock support for i.MX9 platform
Signed-off-by: Yanan Yang <yanan.yang@nxp.com>
Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.com>
Fix CI failure: LEADING_SPACE: please, no spaces at the start of a line
Split code format fixing into a new patch
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Fix wrong case when Flash was called "data" and SRAM was called "code".
Rename Flash to "code" and SRAM to "data".
Signed-off-by: Yuriy Vynnychek <Yuriy.Vynnychek-EE@infineon.com>
Add support for the RISC-V Smcsrind extension, which provides
indirect access to CSRs through the MISELECT and MIREG registers.
Changes:
- Added CONFIG_RISCV_ISA_EXT_SMCSRIND Kconfig option
- Implemented 4 helper functions for indirect CSR access:
* icsr_read/write - basic access
* icsr_read_set/clear - bit manipulation
- Defined 7 CSR registers (MISELECT, MIREG, MIREG2-6)
This is a CSR-only extension that does not require any compiler
support or march flags. The helper functions compile to standard
CSR instructions and work with any toolchain that supports Zicsr.
Primary use case: RISC-V AIA (Advanced Interrupt Architecture)
uses indirect CSRs to access IMSIC (Incoming MSI Controller)
registers.
Signed-off-by: Afonso Oliveira <afonsoo@synopsys.com>
The driver currently provides no way to use Dual IO Read and Single IO
for the rest of the commands currently, and would erroneously use
Single IO PP command in Dual IO mode. This PR fixes and adds
support for that.
Signed-off-by: Utsav Munendra <utsavm@meta.com>
Remove the Boolean tracking of MSPI IO mode as we can now rely on
tracking the entire dev config applied to the MSPI device, multiple
of which will exist in later commits.
Signed-off-by: Utsav Munendra <utsavm@meta.com>
Also in preparation for allowing control command frequency to be
different from the read/write frequency and initialization frequency.
Signed-off-by: Utsav Munendra <utsavm@meta.com>
Instead of just tracking in a bool whether the MSPI device is in
Standard MSPI vs. QPI/OPI config, track the entire MSPI config which was
last applied. This makes it easier later to track more than two configs
to apply based on the next command to transceive.
Signed-off-by: Utsav Munendra <utsavm@meta.com>
Adds a new test suite to verify the behavior of `riscv_pmp_clear_all()`.
These tests ensure that the function correctly clears all unlocked PMP
entries while preserving any entries that are locked.
Signed-off-by: Firas Sammoura <fsammoura@google.com>
Introduce the new function `riscv_pmp_clear_all()` to reset the Physical
Memory Protection (PMP) configuration.
This function iterates through all configured PMP slots. For each entry,
it writes 0x0 to the entry's 8-bit configuration register. This action
attempts to clear all fields, including the Address Matching Mode (A) bits
(setting the region type to OFF), the permission bits (R, W, X), and
the Lock (L) bit.
According to the RISC-V specification, any writes to the configuration
or address registers of a locked PMP entry are ignored. Thus, locked
entries will remain unchanged, while all non-locked entries will be
effectively disabled and their permissions cleared.
The function ensures it operates in Machine mode with MSTATUS.MPRV = 0
and MSTATUS.MPP = M-mode before modifying any PMP Control and Status
Registers (CSRs).
This provides a mechanism to clear all non-locked PMP regions,
returning them to a default disabled state. The function declaration is
exposed in the `include/zephyr/arch/riscv/pmp.h` header file, making it
available for inclusion and use by external modules.
It is recommended for firmware to call this function before transitioning
from a Read-Only (RO) stage to a Read-Write (RW) stage. This ensures
that any PMP settings established during the RO phase, which might no
longer be appropriate, are cleared, providing a clean and secure base
PMP configuration for the RW firmware.
Signed-off-by: Firas Sammoura <fsammoura@google.com>
Adds retained_mem api to espressif deep_sleep sample and enables it for the
following platforms:
- esp32_devkitm/esp32/procpu
- esp32c3_devkitm
- esp32c6_devkitc/esp32c6/hpcore
- esp32h2_devkitm
- esp32s2_devkitc
- esp32s3_devkitm/esp32s3/procpu
Signed-off-by: Marcio Ribeiro <marcio.ribeiro@espressif.com>
Enables retained_mem api test using RTC RAM for the following platforms:
- esp32_devkitc/esp32/procpu
- esp32c3_devkitm
- esp32c6_devkitc/esp32c6/hpcore
- esp32h2_devkitm
- esp32s2_devkitc
- esp32s3_devkitm/esp32s3/procpu
Signed-off-by: Marcio Ribeiro <marcio.ribeiro@espressif.com>
Adds separate memory regions for rtc ram memory areas and reworks linker
scripts to make use of their starting addresses and lengths
Signed-off-by: Marcio Ribeiro <marcio.ribeiro@espressif.com>
Add configuration for the VSYS target regulation voltage.
Explicitly specify the threshold at which charging will resume, instead
of deriving it from the combination of two devicetree properties which
have no compile-time validation.
Simplify the process of initialising the chip by precomputing the
register values and explicitly writing the whole register, instead of
updating multiple fields individually.
Signed-off-by: Jordan Yates <jordan@embeint.com>
Instead of text in the description that specifies the valid values,
add the `enum` property so values are validated at compile time.
Signed-off-by: Jordan Yates <jordan@embeint.com>
Rename the bq25180 implementation and files to the more generic bq2518x.
This charger family contains the bq25180, bq25186, bq25188 and the
standalone (non-I2C) bq25185.
The register maps are practically identical, so the driver should be
re-used.
Signed-off-by: Jordan Yates <jordan@embeint.com>
Adds a test that checks that the network message cache differentiates
between PDUs with the same SRC and SEQ but different NetKey Index.
Signed-off-by: Omkar Kulkarni <omkar.kulkarni@nordicsemi.no>
Improve the network message cache to be aware of network keys to
prevent false duplicate detection across different subnets. This
ensures that messages with the same source address and sequence
number but from different network keys are not incorrectly
identified as duplicates, as it can happen in certain cases.
See ES-26350.
Signed-off-by: Omkar Kulkarni <omkar.kulkarni@nordicsemi.no>
Add full support for all remaining AVRCP vendor-dependent PDUs on both
Controller (CT) and Target (TG), including APIs, callbacks, and shell
commands for testing.
Signed-off-by: Make Shi <make.shi@nxp.com>
Implement support for AVRCP Player app Settings PDUs on both CT/TG
- Added APIs for sending and handling commands like LIST_ATTRS,
LIST_VALS, GET_CURR_VAL, SET_VAL, and related text/inform PDUs.
- Added callbacks for TG request handling and CT response processing.
- Add shell commands for Player app Settings commands testing.
Signed-off-by: Make Shi <make.shi@nxp.com>
This patch adds AVRCP notification event handling for both CT and
TG roles. Also add Shell command support for testing notification
registration and responses.
Signed-off-by: Make Shi <make.shi@nxp.com>
This patch introduces support for AVRCP vendor-dependent commands and
responses, including full handling of fragmented messages.
- Adds fragmentation and reassembly logic for AVRCP vendor-dependent
- Introduces TX queue management using delayed work for TG
- Adds support for GetCapabilities PDUs
- Add new Kconfig for vendor-dependent with fragmentation support
Signed-off-by: Make Shi <make.shi@nxp.com>
Remove unnecessary checking for net_buf_tailroom(buf) < chunk_size
before sending data in avctp_tx_processor.
Signed-off-by: Make Shi <make.shi@nxp.com>
The STM32MP135F-DK board embeds 2 ethernets. Enable the ethernet1
in RMII mode with associated PHY.
Signed-off-by: Arnaud Pouliquen <arnaud.pouliquen@foss.st.com>
Signed-off-by: Arif Balik <arifbalik@outlook.com>
