Added integration_toolchains to allow building/testing with multiple
toolchains available in the environment.
This changes the output structure and adds another level in the path
under twister_out signifying the toolchain used. The toolchain used
(variant) is also part of the json output now.
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
The default SCK and COPI/MOSI pins on the Sparkfun Pro Micro RP2040
board correspond to `GPIO22` and `GPIO23` respectively[^1].
The existing pinctrl definitions in the `spi0_default` don't reflect
this (rather, they match the pinout of the Adafruit KB2040 MCU[^2]).
Update the board's respective pinctrl definitions to match the pinout.
[^1]: https://cdn.sparkfun.com/assets/e/2/7/6/b/ProMicroRP2040_Graphical_Datasheet.pdf
[^2]: https://learn.adafruit.com/assets/106984
Signed-off-by: Anant Thazhemadam <anant.thazhemadam@gmail.com>
Add a new extension config value so that repo URL is not hardcoded in
the extension code.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
Some comprehensive lists were hard to read, improve the code a bit so
that things make more sense.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
Modify the extension so that multiple Doxygen projects can be
referenced. While not required in upstream Zephyr, other users
downstream may require support for this feature.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
Modify the extension so that multiple Doxygen projects can be added.
While not required in upstream Zephyr, other users downstream may
require support for this feature.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
The extension had a some major design flaws, mainly:
- Ignored the `api_overview_doxygen_xml_dir` setting, instead it
"sniffed" doxyrunner properties, so violating environment boundaries
- Computation of Doxygen HTML path worked because of the hardcoded URL
in relative form found in doc/conf.py
This patch moves most code to the actual directive, so that context can
be obtained from the document being parsed. Also, the only config
required now is the Doxygen output dir, obtained from doxyrunner at
conf.py level.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
By default OpenThread uses storage API to store configuration options.
On for example mimxrt1020_evk the enabled by default is
CONFIG_SETTINGS_NONE when CONFIG_SETTINGS is enabled. Fix this problem by
using the CONFIG_SETTINGS_NVS=y.
Signed-off-by: Lukasz Majewski <lukma@denx.de>
Enable execution of i2c driver tests by adding i2c entry to
the list of supported peripherals.
Signed-off-by: Sebastian Głąb <sebastian.glab@nordicsemi.no>
Fixes issue introduced in #76460
The previous code attempted to detect whether TMAG5273 or TMAG3001 was
connected based on DEVICE ID register. This doesn't work as the bits that
denote the version on one part are undefined on the other part, and cannot
be relied on to be zero.
This commit adds a TMAG3001 compatible which (for now) is just derived from
the TMAG5273 compatible. This allows TMAG3001 to be specified directly in
the DT. The driver code is updated to support both compatibles.
Signed-off-by: Yiding Jia <yiding.jia@gmail.com>
The three sensor channels listed below were recently added by the commit
9471df95a5:
- SENSOR_CHAN_GAME_ROTATION_VECTOR
- SENSOR_CHAN_GRAVITY_VECTOR
- SENSOR_CHAN_GBIAS_XYZ
Theses channel names are missing and causes a system crash if the
SENSOR_LOG_LEVEL is set to DEBUG.
Also, the two sensor attributes SENSOR_ATTR_GAIN and SENSOR_ATTR_RESOLUTION
were added by the commit f849140de7.
This adds these missing channel and attribute to the list of names in the
sensor shell.
Signed-off-by: Gaël PORTAY <gael.portay@rtone.fr>
Update the driver to take the "vrefint-cal-resolution" property into
account when performing the calculations.
Signed-off-by: Mathieu Choplain <mathieu.choplain@st.com>
After updating the "st,stm32-vref" binding with a new property containing
the calibration data resolution ("vrefint-cal-resolution"), update the
corresponding nodes in SoC DTSI files with the proper value.
Note that the property is not set on SoCs with resolution of 12, as it is
the default value specified for the property in the binding.
Signed-off-by: Mathieu Choplain <mathieu.choplain@st.com>
Add a property holding calibration resolution, similar to what already
exists in the st,stm32-temp-cal-common binding.
Signed-off-by: Mathieu Choplain <mathieu.choplain@st.com>
The CCP API for the Call Control Profile works on top of the
TBS API, and will eventually replace parts of the TBS API.
Signed-off-by: Emil Gydesen <emil.gydesen@nordicsemi.no>
The previous re-organization has the zephyr-keep-sorted defines
missing. Add them for the I2C drivers and targets. Also
moved lines to fix out-of-order violations.
Signed-off-by: Daniel Schultz <d.schultz@phytec.de>
Remove v3.6 from the list of supported releases. Zephyr v3.6.0 reached
end-of-life on 2024-11-29.
Fixes: ea8bd5a09a
Signed-off-by: Henrik Brix Andersen <henrik@brixandersen.dk>
Since "JLink.exe" is also an executable distributed with JDK's, do an
explicit search on the standard SEGGER install directories for a JTAG
"JLink.exe" before falling back to whatever is first on PATH.
Fixes#51825.
Signed-off-by: Jordan Yates <jordan@embeint.com>
After writing option bytes, force them to be loaded. Failing to perform
this step means the values are never applied and not actually written
to non-volatile memory.
Signed-off-by: Jordan Yates <jordan@embeint.com>
Fixes issue #83555, where UART transmit operations fail in Zephyr
sysbuild projects using MCUboot and the asynchronous UART API
(`CONFIG_UART_ASYNC_API=y`) on SAM0 devices such as the
ATSAMC21G18A.
The issue occurs because the DMA controller is not reset during
initialization, causing `BASEADDR` and `WRBADDR` registers to retain
MCUboot's configuration. This prevents the application from reconfiguring
these registers to its own RAM addresses, leading to UART transmit
timeouts and triggering the `UART_TX_ABORTED` callback.
This patch resolves the issue by resetting the DMA controller during
initialization in `dma_sam0.c`. The following actions are performed:
- Disables the DMA and CRC modules.
- Applies a software reset to ensure a clean state for reconfiguration.
With this change, UART transmit operations work as expected, improving
stability and compatibility between MCUboot and the application.
Signed-off-by: Tristen Pierson <tpierson@electrohire.com>
Refactor the devicetree files for the Atmel SAM E70 and SAM V71 product
series. These SoCs are part of a larger product family (SAM
E70/S70/V70/V71) and share a common set of peripherals.
Introduce a base samx7x.dtsi for all members of the family, containing the
union of all supported peripherals. Specific product series can use
/delete-node/ in their DTSI (e.g. same70.dtsi) for removing peripherals not
present in that product series.
Replace pin-count-specific DTSI files (e.g. same70q19b.dtsi) with
pin-count-agnostic DTSI files (e.g. same70x19b.dtsi) as the pin-count is
not taken into account in these anyways, and adjust the relevant board
devicetrees accordingly.
As part of this refactoring, introduce support for the missing flash memory
density variants of the SAM E70 product series.
Support for the two remaining product series (SAM S70/V70) is not part of
this refactoring as these will require further changes to the SoC support
code (soc/atmel/sam/).
Signed-off-by: Henrik Brix Andersen <henrik@brixandersen.dk>
qemu_x86/atom was failing tests/posix/fs in
test_fs_readdir_threadsafe for some reason and only for that
platform.
All other platforms pass the testsuite properly with the dirent
declared on the stack.
Declare the dirent object statically so that qemu_x86/atom will
pass test cases.
Signed-off-by: Chris Friedt <cfriedt@tenstorrent.com>
DIR is a POSIX type defined via the dirent.h header.
In Zephyr, we define it as `typedef void DIR`, since it is only
ever described via a pointer (much like `FILE`).
However, in checkpatch.pl, functions that return DIR* or accept
a DIR* argument are met with an error of the form below:
```
ERROR:SPACING: need consistent spacing around '*' (ctx:WxV)
```
Examples that trigger this false positive are, for example
```cpp
int dirfd(DIR *dirp);
DIR *fdopendir(int fd);
```
Include `DIR` as a class of specific POSIX types that should be
matched as types rather than other tokens.
Signed-off-by: Chris Friedt <cfriedt@tenstorrent.com>
Declare _POSIX_C_SOURCE in a consistent way for both the
posix/options library as well as the tests/posix/fs
testsuite.
Signed-off-by: Chris Friedt <cfriedt@tenstorrent.com>
The heap and stack are now consistent with other ESP32-C3 boards in
tree. This is necessary for Bluetooth to not crash on boot.
Signed-off-by: Xudong Zheng <7pkvm5aw@slicealias.com>
This is a squash of all the groundwork needed to
get a functioning driver for the DS3231 with the RTC API.
Signed-off-by: Gergo Vari <work@gergovari.com>
If a time-intensive task (like coredump storage over logging interface)
is run in the task watchdog callback, the hardware watchdog might
reset the system before the task finishes.
Increasing the delay from 1s to 10s, which should be sufficient for any
use case.
Signed-off-by: Martin Jäger <martin@libre.solar>
Add CONFIG_SECOND_CORE_MCUX_LAUNCHER. This Kconfig is only enabled when
using sysbuild targeting the Cortex-M4 core on the RT11xx series, and
results in loading a minimal application to the Cortex-M7 core that
boots the Cortex-M4 core. This makes developing on the M4 core simpler,
as the user can now simply target the core with sysbuild enabled and
flashing the application will work as expected.
Signed-off-by: Daniel DeGrasse <daniel@degrasse.com>
OCRAM region in Cortex-M4 memory map at 0x2020_0000 is simply an alias
to the M4 TCM at 0x1FFE_0000, which the zephyr,flash node was previously
set to. Using this base address for OCRAM allows the base address to
match the one used in the M7 memory map, which simplifies loading the M4
image from flash into RAM in the M7 init routine
Signed-off-by: Daniel DeGrasse <daniel@degrasse.com>
Since commit bda8ae8c3f ("drivers: clock_control: silabs: Add clock
control driver"), clock configuration is defined in Device Tree.
We can drop now unused configurations existing in board definitions.
Signed-off-by: Jérôme Pouiller <jerome.pouiller@silabs.com>
Silabs Series-2 (all the EFR32xg2x chips) use the new clock driver
introduced in commit bda8ae8c3f ("drivers: clock_control: silabs: Add
clock control driver"). This driver get all the configuration from the
Device Tree.
The CMU (Clock Management Unit) options (CMU_HFXO_FREQ, CMU_HFRCO_FREQ,
CMU_NEED_LFXO, CMU_HFCLK_HFXO, etc...) are now only used for Series-0
and Series-1. It does not make sense to bother the users with them.
Signed-off-by: Jérôme Pouiller <jerome.pouiller@silabs.com>
It would time out when run on-device due to the NVS setting backend being
incredibly slow once enough entries exist.
Also, rename the tests which use different store implementations to make
that explicit.
Fixes https://github.com/zephyrproject-rtos/zephyr/issues/83210.
Signed-off-by: Tomi Fontanilles <tomi.fontanilles@nordicsemi.no>
Although I/DCACHE aren't included under cm33 architecture,
NXP design and integrate Code Cache/Sys Cache for cm33 to
speed up the core execution efficiency.
For the convenience of developers, we believe that software
developers can directly use Code/Sys Cache as arm's I/D Cache.
Signed-off-by: Lucien Zhao <lucien.zhao@nxp.com>
