This patch makes the following improvements:
- Helper APIs for simplifying RTIO transfers.
- Simplify RTIO Streaming implementation to reduce processing time.
- Add streaming mode atomic state, in order to track overruning the
callback events generation.
- Add device pointer address to logging on error-occurrences, as it is
useful when the app has multiple instances of the driver (e.g: NXP's
VMU RT1170 has two).
Signed-off-by: Luis Ubieda <luisf@croxel.com>
Wait until the trigger or streaming mode is configured. Otherwise,
rebooting in-between runs may cause multiple callbacks invoked when
the trigger may have not been enabled yet.
Signed-off-by: Luis Ubieda <luisf@croxel.com>
This induces extra-cycles in the encoding path while streaming, which
make it difficult to achieve high-bandidth performance. The use-case
being dealt with involves cranking the IMU at 8000 ODR in batches of
1.25 ms (10 samples at 800 Hz).
Signed-off-by: Luis Ubieda <luisf@croxel.com>
As it introduces latencies due to switching to the threads pool.
Moreover, this is not required for streaming as it executes in a
non-blocking path.
Signed-off-by: Luis Ubieda <luisf@croxel.com>
Based on performance observed when cranking the sensor at +1000 Hz ODR,
otherwise is not able to keep up with the pace.
Signed-off-by: Luis Ubieda <luisf@croxel.com>
Microchip MEC SoC's include an interrupt aggregator affecting
the routing of interrupt to the ARM NVIC. IA can not be treated
as a true second level interrupt controller. All interrupt sources
with the exception of GPIOs and eSPI virtual wires can be routed
by IA to individial NVIC inputs. Each bank of GPIOs and VWires
are aggregated into a single NVIC input per bank. For the NVIC
to receive the interrupt signal the respective GIRQ enable must
be set. We attempted to add this informatation by encoding the
DT irq property. This exeperiment failed due to how Zephyr
builds the interrupt tables and MEC IA is not a true second
level interrupt controller. Therefore, drivers for MEC peripherals
need to GIRQ number and bit position to pass to HAL API's or
if a driver is implemented in the linux style without using
the full MEC HAL the GIRQ information is present in DT.
Signed-off-by: Scott Worley <scott.worley@microchip.com>
Previous commit made the input buffer of the hash packet constant.
Let's therefore adapt typing where used, and remove inappropriate
casts of constant buffers to non-constant ones.
All the "backend" hashing functions already take a constant input,
these changes only affect the "plumbing" between the Zephyr crypto
API and the actual implementation where applicable.
Signed-off-by: Titouan Christophe <titouan.christophe@mind.be>
Hashing takes an input buffer, and writes the result in a separate
output buffer. Therefore, the input can be marked as constant, so that
constants can be supplied directly to the hashing context without any
intermediate copy, and without having to perform a type-unsafe cast
from (const uint8_t *) to (uint8_t *)
Signed-off-by: Titouan Christophe <titouan.christophe@mind.be>
- create 'mcxe' as family and 'mcxe24x' as series
- add pinctrl_soc.h
- add soc.c/.h to do system initialization
- Support flash boot if CONFIG_MCXE_FLASH_CONFIG==1
Signed-off-by: Lucien Zhao <lucien.zhao@nxp.com>
- add clock_init function to initialize clock sources according
devicetree settings
- finish basic clock api function
Signed-off-by: Lucien Zhao <lucien.zhao@nxp.com>
Adding files to allow running the following tests for the Infineon
HPPASS SAR ADC driver on the PSOC C3 family of MCUs:
* tests/drivers/adc/adc_api
* tests/drivers/adc/adc_error_case
Modifies the adc_error_cases test to use add a KConfig option
for the valid resolution.
Signed-off-by: John Batch <john.batch@infineon.com>
Adding files to allow running the following samples for the
Infineon HPPASS SAR ADC driver on the PSOC C3 family of MCUs:
* samples/drivers/adc_dt
* samples/drivers/adc_sequence
Signed-off-by: John Batch <john.batch@infineon.com>
Adds HPPASS SAR ADC driver and HPPASS Analog driver files to support
ADC conversion for the PSOC C3 family of MCUs.
Signed-off-by: John Batch <john.batch@infineon.com>
* Separates HPPASS and HPPASS SAR ADC in the device tree
* Makes HPPASS SAR ADC a child of the HPPASS system to reflect hardware
architecture.
* Adds binding files for HPPASS SAR ADC driver.
Signed-off-by: John Batch <john.batch@infineon.com>
Adds a new kconfig CONFIG_MEM_DOMAIN_HAS_THREAD_LIST so that
only the architectures requiring to keep track of threads in
memory domains will have the necessary list struct inside
the memory domain structs. Saves a few bytes for those arch
not needing this.
Also rename the struct fields to be most descriptive of what
they are.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
It has been observed that, during the switching stress test,
the context switching becomes very slow due to enough CPUs
doing RCW transaction on hardware bus (e.g. spin locks).
Since the number of NOPs are the same for all CPUs, they are
simply entering and exiting the relax loop at the same time,
and hitting the bus with RCW transactions at the same time.
Not exactly a deadlock but it slows down the execution
enough to result in the test timing out. The SoC layer has
added an option to offset the number of NOPs per CPU by
adding the CPU to the number of NOPs. So enabling it for
the Intel ADSP boards to workaround the above mentioned
issue. I haven't encountered another slowdown after turning
on this option. So hopefully this lowers the probability of
that happening such that a simple retry can pass the test.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
This allows adding the CPU ID to the number of NOPs in
the custom arch_spin_relax(). With the same number of NOPs
for all CPUs, it is possible to have them all doing RCW
transactions at the same time over and over again if they
enter and exit the spin relax loop at the same time.
This behavior has been observed when doing lots of context
switching, like in the SMP switching stress test. So adds
a new kconfig to fine tune the relax loop behavior if
needed. The new kconfig allows adding the CPU ID to
the number of NOPs which will add some minimal offsetting
to workaround the above mentioned situation.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
Add some content in the testusb sample's README to provide a few more hints
that can be handy for USB newcomers trying to get the sample running along
with testusb.
Signed-off-by: Mathieu Choplain <mathieu.choplain-ext@st.com>
Provide kconfig conf file to set timing parameters.
Provide overlay file for QTMR channel and pin configuration.
Signed-off-by: Felix Wang <fei.wang_3@nxp.com>
Move TEST_PWM_PERIOD and TEST_PWM_PULSE to kconfig
and update macro name with "CONFIG_" prefix.
The default timing parameters may be too big for timer
peripheral, because they have high frequence, can not
generate such slow PWM wave.
To keep compatibility, the default value in kconfig
are consistent with the code.
Signed-off-by: Felix Wang <fei.wang_3@nxp.com>
The mcux_qtmr_pwm_set_cycles can not set 100% and 0%
duty cycle PWM wave.
Set output compare setting based on pulse_cycles and
period_cycles:
1. If pulse_cycles is 0, generate 0% duty cycle wave.
2. If pulse_cycles equals period_cycles but not 0,
generate 100% duty cycle wave.
3. Otherwise toggle output when compare value matched.
Signed-off-by: Felix Wang <fei.wang_3@nxp.com>
This covers both Read-Decode and Streaming mode. Since we haven't had
it there have been a few issues (addressed prior to this commit). From
now on, we should maintain this test similar to the others.
Signed-off-by: Luis Ubieda <luisf@croxel.com>
... when CONFIG_DEMAND_PAGING_ALLOW_IRQ is set.
Found during code inspection. k_mem_page_frame_evict() is otherwise
rarely used,
Signed-off-by: Nicolas Pitre <npitre@baylibre.com>
The benchmark_sync test produces incorrect results on SMP systems due to
a race condition between the producer thread and subscriber threads that
only occurs with parallel execution.
Thread configuration:
- Producer thread: priority 5 (lower priority, runs later)
- Subscriber threads (8): priority 3 (higher priority, runs first)
Expected behavior on uniprocessor:
1. Producer publishes message
2. Subscriber immediately preempts producer (priority 3 < 5)
3. Subscriber processes message, calls atomic_add(&count, 256)
4. Producer resumes, continues to next message
Result: All messages counted before producer checks final count.
Race condition on SMP:
CPU 0 (Producer): CPU 1-3 (Subscribers):
----------------- ----------------------
Publish msg 1
k_msgq_put(sub1) ✓
k_msgq_get() → processing
Publish msg 2
k_msgq_put(sub2) ✓
k_msgq_get() → processing
...continues...
Publish msg 128 ✓
atomic_get(&count) Still processing...
→ Reports incomplete count! atomic_add() comes later
On SMP, the producer doesn't get preempted since it runs on a different
CPU from the subscribers. It races ahead and checks atomic_get(&count)
while subscriber threads on other CPUs are still processing messages.
Observed results:
- Non-SMP: Bytes sent = 262144, received = 262144 ✓
- SMP: Bytes sent = 262144, received = 260352 ✗ (7 messages lost)
This is a benchmark test design issue, not a zbus bug. The test assumes
subscribers complete before the producer finishes, which doesn't hold on
SMP systems. Filter SMP configurations from this test variant for now.
Signed-off-by: Nicolas Pitre <npitre@baylibre.com>
The "_too_small" test variants intentionally configure an isolated buffer
pool with only 2 buffers to validate proper error handling when the pool
is exhausted during notification of 16 msg_subscriber observers. These
tests are likely to fail on SMP systems due to a buffer recycling race
condition:
Expected behavior (uniprocessor):
Publisher Thread:
1. Allocate buf1 for bar_msg_sub1 ✓
2. k_fifo_put(sub1_fifo, buf1)
3. Allocate buf2 for bar_msg_sub2 ✓
4. k_fifo_put(sub2_fifo, buf2)
5. Try allocate buf3 for bar_msg_sub3 → FAIL -ENOMEM
Subscriber threads process messages after notification completes,
pool exhausts at subscriber #3 as expected.
SMP race condition:
CPU 0 (Publisher): CPU 1 (bar_msg_sub1): CPU 2 (bar_msg_sub2):
------------------ --------------------- ---------------------
Alloc buf1 ✓
k_fifo_put(sub1, buf1)
k_fifo_get() → buf1
zbus_sub_wait_msg()
net_buf_unref()
→ buf1 FREED!
Alloc buf2 ✓
(reuses buf1!)
k_fifo_put(sub2, buf2)
k_fifo_get() → buf2
net_buf_unref()
→ buf2 FREED!
Alloc buf3 ✓
(reuses buf1 again!)
...continues...
All 16 allocations succeed!
On SMP systems, subscriber threads on other CPUs may consume and free
buffers quickly enough that they are recycled back to the pool before the
publisher's notification loop can exhaust it. The test's assumption that
notification completes before subscribers run does not hold with parallel
execution.
Since this is a test design limitation (not a zbus bug), filter SMP
configurations from these specific test variants rather than attempt to
artificially slow down subscribers or change thread priorities.
Signed-off-by: Nicolas Pitre <npitre@baylibre.com>
According to the RM, erasing must be done per sector. So, the start
address and the size of an erase operation must be a multiple of 8192
bytes. So, the erase-block-size should be 8192 bytes.
Programming can be done per phrase (start address and size a multiple
of 16 bytes). So, write-block-size should be 16 bytes.
Signed-off-by: Allen Zhang <chunfeng.zhang@nxp.com>
Adds support for the USB device binding for MCTP. Binding created based on
the DMTF specification for USB Transport Binding. The overall design of
this binding follows the existing UART and I2C+GPIO bindings that already
exist in Zephyr.
Signed-off-by: Eric Ocasio <eric.ocasio@nxp.com>
