AIN9 source needs special handling (all from AIN8-AIN14). Conversion
result needs to be scaled up by 3.6 additionally to gain and reference
voltage. In order to achieve correct value in the sample vref-mv is
used as reference voltage instead of predefined internal reference
source.
Signed-off-by: Krzysztof Chruściński <krzysztof.chruscinski@nordicsemi.no>
Sample is reading vref-mv property to get reference voltage and then if
reference source is set to ADC_REF_INTERNAL this value is overwritten.
If vref-mv property is provided then it should not be overwritten.
Signed-off-by: Krzysztof Chruściński <krzysztof.chruscinski@nordicsemi.no>
On nrf54h20 there are additional analog pins (AIN8+). When differential
mode is used they must not be mixed with AIN0-AIN7. Add build time
validation which detects if configuration is invalid.
Signed-off-by: Krzysztof Chruściński <krzysztof.chruscinski@nordicsemi.no>
Change the ACL buffer sizes to be a higher value than the
default, as that caused some issues with the CIS established
event.
Signed-off-by: Emil Gydesen <emil.gydesen@nordicsemi.no>
Add coverity integration as a SCA variant. This is targetting the
service provided by blackduck to open-source projects available on
scan.coverity.com.
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
The nRF GPIO hardware does not store the initial output value
set resulting from gpio_pin_configure() and thus, when
gpio_get_config() is used, the initial value is not returned.
This commit just reads the output value and sets the INIT
value to match in gpio_get_config().
Signed-off-by: Bjarki Arge Andreasen <bjarki.andreasen@nordicsemi.no>
Since https://github.com/zephyrproject-rtos/zephyr/pull/83114 was merged,
I get twister errors unrelated to my pull requests for the STM32H7S78-DK
(for example https://github.com/zephyrproject-rtos/zephyr/actions/runs/14900504138/job/41851537049#step:12:1369)
This is because the function LL_GetFlashSize() was removed from hal_stm32
on the STM32H7RS series in
e5eba65b76
I am unsure if the removal from hal_stm32 is intentional. If yes, then this
commit should be merged into Zephyr to fix compilation for that target.
Otherwise, hal_stm32 must be patched, Zephyr's west manifest updated, and
this commit can be discarded.
Signed-off-by: Titouan Christophe <titouan.christophe@mind.be>
Add nordic-auko and seov-nordic as collaborators for
Drivers: MFD in MAINTAINERS.yml file.
Signed-off-by: Audun Korneliussen <audun.korneliussen@nordicsemi.no>
Remove gmarull, and add nordic-auko and seov-nordic as maintainers
for Drivers: Regulators in MAINTAINERS.yml file.
Signed-off-by: Audun Korneliussen <audun.korneliussen@nordicsemi.no>
it8xxx2 pwm driver does not handle "pwm-output-frequency" property,
so setting the property in borad.dts is useless.
About PWM output frequency, it can be set by pwm-cells "period",
"pwm-output-frequency" is really redundant.
Signed-off-by: Ruibin Chang <Ruibin.Chang@ite.com.tw>
Instead of obscure linker-file hacks providing dummy definitions before
we have the proper generated k-object lookup functions, provide weak
definitions that will be taken out by the real generated implementations
when they are available.
Signed-off-by: Björn Bergman <bjorn.bergman@iar.com>
Mass renaming is carried out to unify some prefixes and shorten some
macros, making the code easier to maintain and support new devices.
- Rename `int_dev` to `gpio_int_dev` for gpio interrupt
- Rename `eirq` to `ext_irq` for external interrupt
- Rename `gpio_rz_hw_config` to `gpio_rz_flags`
- Rename `p_pm` to `gpio_flags`
- Rename `pre_flags` to `rz_flags`
- Remove `_IOPORT` and `_PIN_CONFIGURE` in some macros
- Rename `GPIO_RZ_PIN_CONFIGURE_GET_FILTER`,
`GPIO_RZ_PIN_CONFIGURE_GET`, `GPIO_RZ_PIN_SPECIAL_FLAG_GET` to
`GPIO_RZ_FLAG_GET_FILTER`, `GPIO_RZ_FLAG_GET_CONFIG`,
`GPIO_RZ_FLAG_GET_SPECIFIC` respectively
Signed-off-by: Nhut Nguyen <nhut.nguyen.kc@renesas.com>
In order to be consistant with other formats bayer formats
recently introduced, rename all 4 8 bit bayer formats with a
S prefix (SBGGR / SRGGB / SGBRG / SGRBG).
Signed-off-by: Alain Volmat <alain.volmat@foss.st.com>
Many cellular modems attempt to negotiate an ACCM value of 0x00000000.
While the PPP driver rejects this by default, it does not propose an
alternative. As a result, some modems default to using 0x00000000 after
LCP negotiation. Because the PPP driver expects all control characters
to be escaped, this causes issues during decoding. This change
negotiates an ACCM value of 0xffffffff to ensure compatibility with such
modems.
Signed-off-by: Vytautas Virvičius <vytautas@virvicius.dev>
Xtensa arch layer has some custom compilation commands to
generate the interrupt dispatchers and the core-isa* files.
However, the include path to find core-isa.h does not work
for Espressif ESP32. So update the mechanism to use correct
path pointing to Espressif HAL when targeting ESP32 family
SoCs.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
Add a missing newline between two groups in the pin control .dtsi
file for the ch32v003evt and the linkw board to comply with style
rules.
Signed-off-by: Miguel Gazquez <miguel.gazquez@bootlin.com>
When PM2 is enabled, it will disable many of the devices, so need to
enable PM policy constraints for this mode also so that device drivers
can work.
Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
This driver doesn't need to do anything in its irq_update
implementation, but add a dummy one so that calls to uart_irq_update
don't fail with -ENOSYS.
Signed-off-by: Robert Hancock <robert.hancock@calian.com>
This driver previously caused an assertion error if non-NULL user_data
was passed to uart_irq_callback_set. Add support for this by storing the
user data and passing it back to the IRQ callback function.
Signed-off-by: Robert Hancock <robert.hancock@calian.com>
Since #84446 it became necessary to enqueue a first video buffer before
performing the transfers. Apply this config change to the sample.
Signed-off-by: Josuah Demangeon <me@josuah.net>
The WCH CH32V006EVT is an evaluation board for the RISC-V based
CH32V006K8U6 SOC.
The board is equipped with a power LED, reset button, USB port for
power, and two user LEDs.
Add the board definition, documentation, and sample overlay.
Signed-off-by: Michael Hope <michaelh@juju.nz>
The flash latency needs to be configured before switching to the high
speed clock. Set the latency based on the CH32V003 and CH32V00x
reference manual.
Signed-off-by: Michael Hope <michaelh@juju.nz>
Expand the current systick compatibility to include the CH32V00x
series. Change the HAL compatibility to include all of the CH32V
family.
Signed-off-by: Michael Hope <michaelh@juju.nz>
Compared to the CH32V003, the CH32V00x series is an evolution that
uses a different microarchitecture (V2C instead of V2A) and different
pinctrl mappings.
Fork the current qingke_v2a and use the new proposed naming convention.
Signed-off-by: Michael Hope <michaelh@juju.nz>
The CH32V006 is part of the CH32V00x series of 32 bit RISC-V
microcontrollers. This series is an evolution of the CH32V003 which
was used as a basis for this Devicetree definition.
Compared to the CH32V003, thie CH32V006 has an extra GPIO port (PB),
an extra UART (UART2), 8 KiB of RAM, 62 KiB of flash, and uses the
QingKe V2C core.
Signed-off-by: Michael Hope <michaelh@juju.nz>
The CH32V006 and others in the CH32V00x series are an evolution of the
CH32V003 and use different remap offsets for the various peripherals.
In the same way as the CH32V20x, fork the CH32V003 driver and add
CH32V00x support.
Signed-off-by: Michael Hope <michaelh@juju.nz>
The QingKe V2C has an integer multiplier but no divide. Add support
for the corresponding Zmmul extension and, as the extension was added
in GCC 13.0, add a test for the compiler version.
Signed-off-by: Michael Hope <michaelh@juju.nz>
Added 2 different revisions of RPL-s board with 2 PCH
options 600 series and 700 series.
Signed-off-by: Anisetti Avinash Krishna <anisetti.avinash.krishna@intel.com>
