drivers: can: numaker: fix m2l31x core clock
This fixes canfd core clock for m2l31x soc. Signed-off-by: Chun-Chieh Li <ccli8@nuvoton.com>
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1 changed files with 19 additions and 10 deletions
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@ -18,12 +18,6 @@
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LOG_MODULE_REGISTER(can_numaker, CONFIG_CAN_LOG_LEVEL);
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/* CANFD Clock Source Selection */
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#define NUMAKER_CANFD_CLKSEL_HXT 0
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#define NUMAKER_CANFD_CLKSEL_PLL_DIV2 1
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#define NUMAKER_CANFD_CLKSEL_HCLK 2
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#define NUMAKER_CANFD_CLKSEL_HIRC 3
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/* Implementation notes
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* 1. Use Bosch M_CAN driver (m_can) as backend
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* 2. Need to modify can_numaker_get_core_clock() for new SOC support
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@ -55,18 +49,33 @@ static int can_numaker_get_core_clock(const struct device *dev, uint32_t *rate)
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clkdiv_divider = CLK_GetModuleClockDivider(config->clk_modidx) + 1;
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switch (clksrc_rate_idx) {
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case NUMAKER_CANFD_CLKSEL_HXT:
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#if defined(CONFIG_SOC_SERIES_M46X)
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case (CLK_CLKSEL0_CANFD0SEL_HXT >> CLK_CLKSEL0_CANFD0SEL_Pos):
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*rate = __HXT / clkdiv_divider;
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break;
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case NUMAKER_CANFD_CLKSEL_PLL_DIV2:
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case (CLK_CLKSEL0_CANFD0SEL_PLL_DIV2 >> CLK_CLKSEL0_CANFD0SEL_Pos):
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*rate = (CLK_GetPLLClockFreq() / 2) / clkdiv_divider;
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break;
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case NUMAKER_CANFD_CLKSEL_HCLK:
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case (CLK_CLKSEL0_CANFD0SEL_HCLK >> CLK_CLKSEL0_CANFD0SEL_Pos):
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*rate = CLK_GetHCLKFreq() / clkdiv_divider;
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break;
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case NUMAKER_CANFD_CLKSEL_HIRC:
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case (CLK_CLKSEL0_CANFD0SEL_HIRC >> CLK_CLKSEL0_CANFD0SEL_Pos):
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*rate = __HIRC / clkdiv_divider;
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break;
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#elif defined(CONFIG_SOC_SERIES_M2L31X)
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case (CLK_CLKSEL0_CANFD0SEL_HXT >> CLK_CLKSEL0_CANFD0SEL_Pos):
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*rate = __HXT / clkdiv_divider;
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break;
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case (CLK_CLKSEL0_CANFD0SEL_HIRC48M >> CLK_CLKSEL0_CANFD0SEL_Pos):
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*rate = __HIRC48 / clkdiv_divider;
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break;
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case (CLK_CLKSEL0_CANFD0SEL_HCLK >> CLK_CLKSEL0_CANFD0SEL_Pos):
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*rate = CLK_GetHCLKFreq() / clkdiv_divider;
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break;
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case (CLK_CLKSEL0_CANFD0SEL_HIRC >> CLK_CLKSEL0_CANFD0SEL_Pos):
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*rate = __HIRC / clkdiv_divider;
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break;
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#endif
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default:
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LOG_ERR("Invalid clock source rate index");
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return -EIO;
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