drivers: can: numaker: fix m2l31x core clock

This fixes canfd core clock for m2l31x soc.

Signed-off-by: Chun-Chieh Li <ccli8@nuvoton.com>
This commit is contained in:
Chun-Chieh Li 2025-04-22 15:37:30 +08:00 committed by Benjamin Cabé
commit d1e8590b6b

View file

@ -18,12 +18,6 @@
LOG_MODULE_REGISTER(can_numaker, CONFIG_CAN_LOG_LEVEL);
/* CANFD Clock Source Selection */
#define NUMAKER_CANFD_CLKSEL_HXT 0
#define NUMAKER_CANFD_CLKSEL_PLL_DIV2 1
#define NUMAKER_CANFD_CLKSEL_HCLK 2
#define NUMAKER_CANFD_CLKSEL_HIRC 3
/* Implementation notes
* 1. Use Bosch M_CAN driver (m_can) as backend
* 2. Need to modify can_numaker_get_core_clock() for new SOC support
@ -55,18 +49,33 @@ static int can_numaker_get_core_clock(const struct device *dev, uint32_t *rate)
clkdiv_divider = CLK_GetModuleClockDivider(config->clk_modidx) + 1;
switch (clksrc_rate_idx) {
case NUMAKER_CANFD_CLKSEL_HXT:
#if defined(CONFIG_SOC_SERIES_M46X)
case (CLK_CLKSEL0_CANFD0SEL_HXT >> CLK_CLKSEL0_CANFD0SEL_Pos):
*rate = __HXT / clkdiv_divider;
break;
case NUMAKER_CANFD_CLKSEL_PLL_DIV2:
case (CLK_CLKSEL0_CANFD0SEL_PLL_DIV2 >> CLK_CLKSEL0_CANFD0SEL_Pos):
*rate = (CLK_GetPLLClockFreq() / 2) / clkdiv_divider;
break;
case NUMAKER_CANFD_CLKSEL_HCLK:
case (CLK_CLKSEL0_CANFD0SEL_HCLK >> CLK_CLKSEL0_CANFD0SEL_Pos):
*rate = CLK_GetHCLKFreq() / clkdiv_divider;
break;
case NUMAKER_CANFD_CLKSEL_HIRC:
case (CLK_CLKSEL0_CANFD0SEL_HIRC >> CLK_CLKSEL0_CANFD0SEL_Pos):
*rate = __HIRC / clkdiv_divider;
break;
#elif defined(CONFIG_SOC_SERIES_M2L31X)
case (CLK_CLKSEL0_CANFD0SEL_HXT >> CLK_CLKSEL0_CANFD0SEL_Pos):
*rate = __HXT / clkdiv_divider;
break;
case (CLK_CLKSEL0_CANFD0SEL_HIRC48M >> CLK_CLKSEL0_CANFD0SEL_Pos):
*rate = __HIRC48 / clkdiv_divider;
break;
case (CLK_CLKSEL0_CANFD0SEL_HCLK >> CLK_CLKSEL0_CANFD0SEL_Pos):
*rate = CLK_GetHCLKFreq() / clkdiv_divider;
break;
case (CLK_CLKSEL0_CANFD0SEL_HIRC >> CLK_CLKSEL0_CANFD0SEL_Pos):
*rate = __HIRC / clkdiv_divider;
break;
#endif
default:
LOG_ERR("Invalid clock source rate index");
return -EIO;