For better organization, split the Kconfig files into one per each CPU.
Also, there was a bug where MFD was made to depend on flexcomm being
enabled, when really it probably meant to just default y if flexcomm is
enabled.
Leave Kconfig.soc in one file for the SOC.
Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
We can both optimize and clean up the code by using short circuit logic
and static variables instead of stack variables.
Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
Refactor ISR by:
1) making a helper function to put the tickful calculation in, to reduce
an indentation level and cognitively separate this case while reading
2) Rewrite the calculations to simplify them. More info on that below.
Math changes:
- In the ISR, there was a variable called "now" which represented the
current cycle count of the timer. last_count was updated using a
calculation based on the number of elapsed ticks
and the hardware cycles per second value. However, this is
redundant because mathematically, this is equivalent to "now". So the
variable can just be set to now.
Proof is that the previous calculation was (in programming language):
(1) last_count = last_count + elapsed_ticks * CYC_PER_TICK
So let's rewrite this as the following to be clear about the different
values we are talking about here (in math language):
(2) count[t] = count[t-1] + elapsed_ticks * CYC_PER_TICK
We calculated elapsed ticks in the function as:
(3) elapsed_ticks = (now - last_count) / CYC_PER_TICK
(4) elapsed_ticks = (now - count[t-1]) / CYC_PER_TICK
Rearranging (2), we see
(5) elapsed_ticks = ( count[t] - count[t-1] ) / CYC_PER_TICK
Substituting this into (4), we get:
(6) ( count[t] - count[t-1] ) / CYC_PER_TICK =
(now - count[t-1]) / CYC_PER_TICK
Doing simple algebra, you can see we result with:
(7) count[t] = now
So therefore, we can simplify the programming expression to
(8) last_count = now
- The other change is regarding the calculation of the next tick match
value for tickful kernel mode. The previous calculation was doing:
(1) next = now + CYC_PER_TICK
We know that last_count is equivalent to now, at this point in the code
with the first change:
(2) next = last_count + CYC_PER_TICK
And then, for some reason, we are adding yet another CYC_PER_TICK to
next if (next - now) < MIN_DELAY. The reason for that I do not
understand, but let's write that down:
(3) next - now < MIN_DELAY
Now rewrite (2) as (4) and (3) as (5):
(4) count[t+1] = count[t] + CYC_PER_TICK
(5) count[t+1] - count[t] < MIN_DELAY
And now we substitute (4) into (5):
(6) count[t] + CYC_PER_TICK - count[t] < MIN_DELAY
And simplify:
(7) CYC_PER_TICK < MIN_DELAY
So actually no runtime calculations are needed here, this is a
hardcoding. The reason for this calculation I don't know, but we can
simplify the code.
Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
There are a couple places where effectively the exact same calculation
is done. Refactor to share code to do this calculation to make it easier
to read, and explode the code to multiple statements to be even easier
to follow the calculation. Compiler will likely optimize the same way
when opt enabled. Rename dticks variable to be more explicit what that
means (elapsed ticks).
Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
Refactor to remove nesting and consolidate lines of code.
I also ran clang format but that actually did not change very much in
addition to what I had already changed manually.
Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
Some SoCs such as iMX8ULP and iMX93 use sentinel controller
for secure system management, this change ensures the device
driver is available by default.
Signed-off-by: Yongxu Wang <yongxu.wang@nxp.com>
This update ensures that TRDC settings are correctly applied
when user space is enabled. By default, the M33 core operates
in privileged mode.
However, when user threads are scheduled, the system transitions
to unprivileged mode. The TRDC configuration is adjusted to support
this behavior, maintaining secure and functional access control
for both privileged and unprivileged execution contexts.
Signed-off-by: Yongxu Wang <yongxu.wang@nxp.com>
1.Remove the code that sets the UTRIM register to 0,
because UTRIM is automatically loaded with a factory-trimmed
value, zeroing will affect the accuracy. Only need to clear
VREF UTRIM[TRIM2V1] at the initialization stage.
2. VREF does not have NXP_VREF_MODE_INTERNAL_REGULATOR mode,
the internal voltage regulator and chop oscillator are used
to suppress power supply noise and reduce voltage offset,
so remove the NXP_VREF_MODE_INTERNAL_REGULATOR mode.
there are only three modes in VREF, the first is the standby
mode (CSR[BUF21EN] = 0, CSR[HI_PWR_LV] = X), the second is
low power mode (CSR[BUF21EN] = 1, CSR[HI_PWR_LV] = 0), and
the third is high power mode (CSR[BUF21EN] = 1, CSR[HI_PWR_LV] = 1).
Signed-off-by: Zhaoxiang Jin <Zhaoxiang.Jin_1@nxp.com>
1. Added new boolean type 'nxp,internal-voltage-regulator-en'
and 'nxp,chop-oscillator-en' properties for 'nxp,vref'.
The user can use these properties to improve the stability
and accuracy of the VREF output voltage.
2. Added properties 'nxp,current-compensation-en' and
'nxp,internal-voltage-regulator-en' and 'nxp,chop-oscillator-en'
for LPC55S3x, MCXN23x, MCXN94x, and MCXW7x VREF node.
Signed-off-by: Zhaoxiang Jin <Zhaoxiang.Jin_1@nxp.com>
1.The VREFO is internally connected to the ADC channel,
so can change the measurement channel to simplify the
test process.
2.Change the VREF mode to NXP_VREF_MODE_HIGH_POWER as the
'NXP_VREF_MODE_INTERNAL_REGULATOR' mode is removed.
3.Increase ADC sample time to improve ADC accuracy
4.Adjust tolerance-microvolt to a suitable value,
20000uv is a more suitable value for NXP VREF,
the actual VREF tolerance-microvolt can be smaller
than this value, but hardware differences may cause
this case to fail to run on some boards.
5.Add frdm_mcxn236 and frdm_mcxw71 to test platform.
Signed-off-by: Zhaoxiang Jin <Zhaoxiang.Jin_1@nxp.com>
The macros for PWM output on these GPIOs had names that referred to PWM
channels that do no exist on this chip- it only has 12 channels, where
channels 8..11 are exposed on both GPIOs 32..39 and 40..47.
Signed-off-by: Peter Marheine <peter@taricorp.net>
RP2350 adds four more PWM slices from the eight available on RP2040,
which are only broken out to package pins on RP2350B. This change fixes
the driver to support the correct number of slices on RP2350.
Tested by confirming that PWM can correctly be configured on GPIO 44 of
RP2350B.
Signed-off-by: Peter Marheine <peter@taricorp.net>
RP2350 has 48 GPIOs, where only the first 30 are broken out to pins on
RP2350A (same as RP2040) and the remaining 18 are only usable on RP2350B.
This change makes the soc pinctrl driver support GPIOs above 31, where
previously it was impossible to configure GPIOs 32 through 47.
Tested on RP2350B, confirming that GPIO44 can be correctly configured for
PWM.
Signed-off-by: Peter Marheine <peter@taricorp.net>
Updates the implementation of the osEventFlags APIs to use
Zephyr kernel events instead of polling.
Fixes#92899
Signed-off-by: Peter Mitsis <peter.mitsis@intel.com>
Replace direct assignment of evt.evt_data with structured access via
espi_evt_data_pvt. This change separates the incoming evt_data into
type and data fields.
This update alse includes support for handling PVT, PVT2, and PVT3
events using the structured event data.
Signed-off-by: Tim Lin <tim2.lin@ite.corp-partner.google.com>
Introduce a new bit field structure "espi_evt_data_pvt" to represent
the evt_data field in PVT IO related eSPI peripheral events.
With this change, callback functions handling eSPI events can extract
both the data and its associated type from evt_data.
Signed-off-by: Tim Lin <tim2.lin@ite.corp-partner.google.com>
For devices other than the stm32h745/747/755/757 that use
dual-core cortex-M4/cortex-M7, do not multiply flash
controller size by 2. Single-core stm32h7x devices define
their flash-controllers dtsi as a single area, not two banks.
Use the presence of the bank2-flash-size prop to determine if
this is a dual-core stm3h7x or not.
Signed-off-by: Rory Piper <rory.piper@signal-fire.com>
This cleans up the doxygen documentation for the MCUmgr subsystem
(consolidated the doxygen groups, added some missing docs, added proper
@name'd sections where appropriate, etc).
Signed-off-by: Benjamin Cabé <benjamin@zephyrproject.org>
Which does not have HW support for it, as stated by ST here:
https://www.st.com/en/microcontrollers-microprocessors/stm32u575-585.html
"
The STM32U575 portfolio offers from 1 to 2 Mbytes of flash memory
and from 48- to 169-pin packages.
The STM32U585 is available with 2 Mbytes of flash memory and provides
an additional encryption accelerator engine (AES, PKA, and OTFDEC).
"
All the U5 SoC have a hash HW accelerator (even the ones which don't
have crypto support: U535XX, U575XX, U59XXX and U5FXXX).
The hash node is therefore moved directly inside the stm32u5.dtsi.
Signed-off-by: Philémon Jaermann <p.jaermann@gmail.com>
Introduce a new API function in the sdmmc_stm32 driver that allows
applications to access the Card Identification (CID) register of the
SD/MMC card. This functionality, already available in the SPI-based SD
and MMC subsystems, was previously missing from the STM32 SDMMC driver.
This enhancement enables use cases such as verifying the correct SD card
during manufacturing, ensuring that OEMs use the specified SD card, and
preventing mismatches.
Signed-off-by: Arthur Gay <arthur.gay@marshmallow.kids>
This commit adds the i2c8 node to the device tree for the
STM32MP257F-EV1 board. This node corresponds to the i2c exposed by the
GPIO expansion connector [1] and not used by the cortex A35.
[1]: https://wiki.st.com/stm32mpu/wiki/STM32MP257x-EV1_-_hardware_description
Signed-off-by: Tanguy Raufflet <tanguy.raufflet@savoirfairelinux.com>
According to the STM32MP2 reference manual, the I2C controller uses
a single interrupt line for all events (EV + ERR), so the combined
interrupt must be enabled for the STM32MP2 series.
Signed-off-by: Tanguy Raufflet <tanguy.raufflet@savoirfairelinux.com>
The STM32MP2 series needs gpioz pinctrl support to be able to use
the GPIOZ pins.
Signed-off-by: Tanguy Raufflet <tanguy.raufflet@savoirfairelinux.com>
Update hal_stm32 to include the modifications allowing to read the I2C8
clock frequency in the same way as I2C1-7.
Signed-off-by: Tanguy Raufflet <tanguy.raufflet@savoirfairelinux.com>
The Controller is abbreviated as CTLR in contrast to CTRL
which is used in the context of Link Layer Control
Procedures.
Signed-off-by: Vinayak Kariappa Chettimada <vich@nordicsemi.no>
Adding sys_poweroff to WBA family. It switches to standby
(non-retention) mode. It can be woken up by any wakeup source.
Signed-off-by: Ivan Wagner <ivan.wagner@tecinvent.ch>
Enable two timers and PWM in STM32N6570-DK board dts.
Add overlays to test the pwm_loopback test on STM32N6570-DK board.
Signed-off-by: Guillaume Gautier <guillaume.gautier-ext@st.com>
