Now that the timer kernel clocks are defined in device tree, use the
clock get API to fetch the clock frequency instead of calculating the
value in the driver.
Removes the now unused function get_tim_clk.
Signed-off-by: Guillaume Gautier <guillaume.gautier-ext@st.com>
Now that the timer kernel clocks are defined in device tree, use the
clock get API to fetch the clock frequency instead of calculating the
value in the driver.
Removes the now unused function counter_stm32_get_tim_clk.
Signed-off-by: Guillaume Gautier <guillaume.gautier-ext@st.com>
Add support for timer kernel clock for STM32U0.
Contrary to other series, on U0, TIMPCLK is always equal to PCLK, so no
need to define it, we can use PCLK directly.
Signed-off-by: Guillaume Gautier <guillaume.gautier-ext@st.com>
Add support for timer kernel clock for STM32H7RS.
Define a new property for the timer prescaler in the RCC binding of H7RS.
Also fix the clock bus of TIM16 and TIM17 (they are on APB2 instead of 1)
Signed-off-by: Guillaume Gautier <guillaume.gautier-ext@st.com>
Add support for timer kernel clock for STM32H7.
Define a new property for the timer prescaler in the RCC binding of H7.
Signed-off-by: Guillaume Gautier <guillaume.gautier-ext@st.com>
Add support for timer kernel clock for STM32H5.
Define a new RCC binding for H5 with the timer prescaler property (timpre).
Signed-off-by: Guillaume Gautier <guillaume.gautier-ext@st.com>
Add support for timer kernel clock for STM32F7.
The STM32F7 RCC clock driver complies with st,stm32f4-rcc
driver variant.
Signed-off-by: Guillaume Gautier <guillaume.gautier-ext@st.com>
Add support for timer kernel clock for STM32F4.
Define a new RCC binding to add the timer prescaler property (timpre).
This new binding is used for all STM32F4 except F405/F407/F415/F417 who do
not support it.
Signed-off-by: Guillaume Gautier <guillaume.gautier-ext@st.com>
Add support for timer kernel clock for STM32F3.
Also reorganizes the timer instances:
- TIM3 is not available on F301, F318, F302x6 or x8, but is available for
all others
- TIM4 is available on F302xB and higher, F303xB and higher, F358, F398,
F373 and F378
- TIM7 is not available on F301, F318, F302, but is available for all
others
- TIM8 is only available on F303xB and higher, F358 and F398
- TIM20 is only available on F303xD and xE,and on F398
Depending of the SoC version, some timers have access to one or two
distinct clock sources. Timers with NO_SEL selection only have access
to the base TIMPLCKx clock, those defined with TIMx_SEL(0) can use another
source clock: STM32_SRC_TIMPLLCLK. That's why some clocks are redefined.
Signed-off-by: Guillaume Gautier <guillaume.gautier-ext@st.com>
Add note for the new requirement for the GMAP BGS role. There is
no GMAP sample or any changes in-tree that need to be updated for
this, so the best we can do, without implement a whole new sample,
is to refer to the BAP broadcast assistant sample.
Signed-off-by: Emil Gydesen <emil.gydesen@nordicsemi.no>
This helps anchoring the file to the proper section in the online
documentation when browsing by file.
Signed-off-by: Benjamin Cabé <benjamin@zephyrproject.org>
add a missing doc + actually show up the utilities from the gpio_utils.h
header file in the doxygen documentation.
Signed-off-by: Benjamin Cabé <benjamin@zephyrproject.org>
Group the vendor headers into the doxygen group used for device-specific
GPIO API extensions as opposed to have them clutter top-level GPIO docs
Signed-off-by: Benjamin Cabé <benjamin@zephyrproject.org>
Add a new doxygen group for device-specific GPIO API extensions and
put vendor header files in it.
Signed-off-by: Benjamin Cabé <benjamin@zephyrproject.org>
Update BAP unicast server samples to work with Google Pixel:
Fix sink/source location count to match actual sink/source count,
preventing "Codec channel setup fail" errors on phone
Increase ATT prepare count from 1 to 2 to handle phone sending
Codec Config for 3 ASEs simultaneously, avoiding Codec Config
failures during recording
Signed-off-by: Chang An <chang.an_1@nxp.com>
- Code optimization for platforms which don't use subscription feature
in the temperature service.
- Test adaptation to code changes
Signed-off-by: Rafal Dyla <rafal.dyla@nordicsemi.no>
Switch the selects on `LORAWAN_FRAG_TRANSPORT` to `depends on`. `select`
should only be used for simple symbols without dependencies themselves.
Mixing `depends on X` and `select X` on different symbols is the primary
cause of Kconfig dependency loops.
Signed-off-by: Jordan Yates <jordan@embeint.com>
This commit sets the interrupt mode to high-level
triggered, as fifo mode is enabled by default
(CONFIG_SPI_ITE_IT51XXX_FIFO_MODE=y) and the fifo
mode only supports high-level triggered.
Signed-off-by: Ren Chen <Ren.Chen@ite.com.tw>
This commit disables spi clock during idle to reduce power
consumption.
Tested with: reduce current cons. by around 0.08mA on it515xx_evb
Signed-off-by: Ren Chen <Ren.Chen@ite.com.tw>
Enable USB for the Nucleo U385RG-Q. Samples in samples/subsys/usb compile
and operate as expected.
Signed-off-by: Will McGloughlin <willem.mcg@gmail.com>
The loop condition is not the count of the actual tries since the
continue or breaks can occur on the loop and thus a failure count
can falsely match a loop count even when a query is outstanding.
This can be seen when a dual stack resolve is used for IPv4 and IPv6
that has two fds to be used and the interface has only gotten an
IPv6 address. The failures on the IPv4 will indicate a 1 and the break
on the tried attempt on the IPv6 will break the loop on a 1.
Signed-off-by: Charles Hardin <ckhardin@gmail.com>
Add initial support for the ROC-RK3588-PC AArch64 board.
It features a quad-core Cortex-A55 CPU based on the ARMv8.2 architecture.
This commit also enables SMP, allowing all four cores to run the
synchronization sample.
Signed-off-by: Guowei Li <15035660024@163.com>
Add initial device tree support for the Rockchip RK3588 SoC.
The DTS describes:
- Four Cortex-A55 cores with PSCI enable-method
- GICv3 interrupt controller
- ARMv8 timer
- UART2 and UART3 (disabled by default)
Signed-off-by: Guowei Li <15035660024@163.com>
