DDR50/DDR52 modes should use PINCTRL_STATE_SLOW (50MHz), so the lack of a
break statement after enabling DDR mode is expected. Add an explicit
__fallthrough to resolve the issue flagged by coverity scan
Fixes#65324
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Explicitly set host_io fields, instead of using memset(). This way the
fields should have values that are defined in the enum types for each
field.
Fixes#63130
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
This patch enables DSP clock gating for ACE platforms. By default, clock
gating is blocked by the firmware in the hardware configuration. If
CONFIG_ADSP_IDLE_CLOCK_GATING is enabled, this prevent is not active and
clock can be gated when core is in idle state. WIth this option disabled
clock gating will only be enabled in hardware during power gating.
Signed-off-by: Tomasz Leman <tomasz.m.leman@intel.com>
The subsys/logging/logger example can be used to demonstrate how to
use SWO for logging. Add a configuration fragment that enables the
logger's SWO backend. The default SWO frequency in this example is set
to 2 MHz to ensure a well-defined output bit rate instead of the
highest possible.
Signed-off-by: Andreas Sandberg <andreas@sandberg.uk>
The STM32 G4 series has a built-in Arm Instrumentation Trace
Macrocell. Set CONFIG_HAS_SWO to enable this.
Signed-off-by: Andreas Sandberg <andreas@sandberg.uk>
Add new functions to the public CoAP API to configure CoAP packet
retransmission settings. Application may need to re-configure the
settings for example when cellular modem changes connection from
LTE-M to NB-IoT or vice versa.
Signed-off-by: Juha Ylinen <juha.ylinen@nordicsemi.no>
The plic has a very simple mechanism to claim an interrupt as well as to
complete and clear it. The same register is read from/ written to to
achieve this.
Get the ID of the HART that serviced the interrupt and write to the
claim complete register in the correct context
Signed-off-by: Conor Paxton <conor.paxton@microchip.com>
The plic uses contexts to seperate irq enables, threshold priority and
claim complete registers from each core for a given platform. As well as
this, each privilege level has its own context.
for multi-core platform's, we need to be able to enable/ disable a
global interrupt for all the cores that are associated with Zephyr.
To do this, we need to make some assumptions:
1. The privilege contexts are contiguous
2. M mode context is first, followed by S mode.
We know how many cpus are used in an application and each cpu's hartid,
thanks to some very handy inline functions. So we iterate through each
cpu and use the hartid of a cpu in the calculation of the context.
While we are at it, In an effort to make the driver more readable,
allign with the macro naming convention outlined in Linux's PLIC driver
Signed-off-by: Conor Paxton <conor.paxton@microchip.com>
Assuming that all supported releases require at least CMake
version 3.0, we should be able to calculate the md5sum in a
much simpler way using string().
https://cmake.org/cmake/help/v3.0/command/string.html
This avoids writing a temporary file into the source directory
and therefore mitigates the possibility of the following
warning.
share/zephyr-package/cmake/zephyr_export.cmake:19 (string):
string sub-command SUBSTRING requires four arguments.
Signed-off-by: Christopher Friedt <cfriedt@meta.com>
Set the prescaler for the stm32_lp_tick_source lptim node.
When the LPTIM is clocked by the LSE with a prescaler
of 16 (lptim freq at 2048Hz) expecting 2048 for the TICKS_PER_SEC.
When the LPTIM is clocked by the LSE with a prescaler
of 32 (lptim freq at 1024Hz) expecting 1024 for the TICKS_PER_SEC.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
Update migration guide to introduce the stm32_lp_tick_source
for stm32 device when choosing the LPTIM fo lowPower modes.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
Change the name of the node for the lptim used as lowpower
tick source to stm32_lp_tick_source.
Once enabled, this node is known as stm32_lp_tick_source
That will avoid naming the node lptim1 or lptim2 or lptim, etc.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
Configure the SYS_CLOCK_TICKS_PER_SEC directly from the
DTS st-prescaler property of the lptim node
aka stm32_lp_tick_source
Signed-off-by: Francois Ramu <francois.ramu@st.com>
With low LPTIM freq when prescaler is set to 16 or 32,
the CONFIG_SYS_CLOCK_TICKS_PER_SEC must be reduced to
LPTIM CLOCK_/prescaler to avoid spurious timer wakeup activity.
Assert error if the CONFIG_SYS_CLOCK_TICKS_PER_SEC
is not compatible with the lptim clock freq.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
Rename to LPTIM_PRESCALER, the <st,property> prescaler of
the stm32 LPTimer. This commit gives better readability than
LPTIM_CLOCK_RATIO.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
The commit fixes the SHA driver because the ROM API has the following
changes from ES to QS chip:
1. base addres: from 0x13c -> 0x148
2. required SHA context buffer size : from 228 -> 240 bytes
This change also adds a check for the pre-allocated buffer size of the
SHA context when the driver initiliazes.
Signed-off-by: Jun Lin <CHLin56@nuvoton.com>
The instruction cache in the STM32F7 and H7 was enabled regardless
of the value assigned via Kconfig to the CONFIG_ICACHE parameter.
This commit adds the missing conditional checks; note that this does
not affect the compiled behavior unless CONFIG_ICACHE is explicitly
disabled by the user.
Remove a redundant low-level check on DCache being already enabled,
since it is also performed inside the SCB_EnableDCache function.
Signed-off-by: Luca Burelli <l.burelli@arduino.cc>
Remove BT_SPI_BLUENRG Kconfig parameter as it is redundant according to
the new changes introduced by ST SPI protocol V1 and V2.
Remove "config BT_SPI_BLUENRG" from the boards that were using it.
Signed-off-by: Ali Hozhabri <ali.hozhabri@st.com>
Introduce STMicroelectronics SPI protocol V2 which is used in BlueNRG-1
and successor devices.
Change the size of the variable "size" to 16 bits as it is necessary for ST
BlueNRG-1 and successor devices.
Signed-off-by: Ali Hozhabri <ali.hozhabri@st.com>
Replace the header acquisition scope in bt_spi_send with bt_spi_get_header.
Add WRITE_DATA_CONDITION in order not to retransmit data without reading
the header as it is meaningless for ST BlueNRG devices.
Signed-off-by: Ali Hozhabri <ali.hozhabri@st.com>
Update structure of spi.c to have a better and cleaner separation
between STMicroelectronics and Zephyr SPI protocol.
Introduce bt_spi_get_header to separate algorithms well for
header acquisition in different protocols.
Remove header acquisition from bt_spi_rx_thread to make it simpler.
Signed-off-by: Ali Hozhabri <ali.hozhabri@st.com>
Add "st,hci-spi-v1.yaml" to represent STMicroelectronics SPI protocol V1
which is used by BlueNRG-MS devices.
Add "st,hci-spi-v2.yaml" to show STMicroelectronics SPI protocol V2
utilized by BlueNRG-1 and successor devices.
Signed-off-by: Ali Hozhabri <ali.hozhabri@st.com>
Multilevel interrupt configs are leaking into every single build without
this option being enabled, so guard the Kconfig and include files to
avoid this.
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
This fixes issue where API use is able to register writable preset even
if the CONFIG_BT_HAS_PRESET_NAME_DYNAMIC Kconfig option was disabled.
Signed-off-by: Mariusz Skamra <mariusz.skamra@codecoup.pl>
The macro returned the wrong value for any case in which
num_bits<=0, due to a signed/unsigned division. The num_bits=0 case was
hit using static analysis in a Nordic Semiconductor SDK case.
Signed-off-by: Burt Silverman <burtms@gmail.com>
Update prompt for profile type not set, make it appear in a similar
way as the rest of the options in the choice.
Add in parethesis "base", which is how this referred to in the upstream
TF-M documentation.
Signed-off-by: Joakim Andersson <joakim.andersson@nordicsemi.no>
