This adds a base binding for I3C controllers.
Note that this follows the Linux kernel 5.17 bindings under
Documentation/devicetree/bindings/i3c/i3c.yaml.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
This adds a few bits to the devicetree API tests for multi-bus
nodes where a bus can support multiple protocols. This uses
I3C as basis as I3C controller can support both I2C and I3C on
the same bus, while I2C controller cannot support both. So
this needs to make sure the correct bus macros are generated
if appropriate (and not generated if not needed).
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
For a single bus that supports multiple protocols, e.g. I3C and I2C,
the single value "bus:" setting is no longer sufficient, as a I3C bus
cannot be matched to a device having "on-bus: I2C". This commit
extends the "bus:" setting so that it can accept a list of values.
This change allows corresponding devicetree macros to be generated
so that DT_ON_BUS() can work properly in this scenario.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
Interrupt vectors level 5 and 6 are not available in ACE. Just remove
them from the linker script.
Signed-off-by: Flavio Ceolin <flavio.ceolin@intel.com>
In ace15_mtpm the debug exception vector address is mapped to INTLEVEL4
and not INTLEVEL 6. This can be checked in the core-isa header:
"""
define XCHAL_DEBUG_VECTOR_VADDR XCHAL_INTLEVEL4_VECTOR_VADDR
"""
in
modules/hal/xtensa/zephyr/soc/intel_ace15_mtpm/xtensa/config/core-isa.h
Signed-off-by: Flavio Ceolin <flavio.ceolin@intel.com>
The pan1782 module on the evaluation board will not longer be available
with external oscillator, so the internal RC must be used by default
for the slow clock.
Signed-off-by: Steffen Jahnke <steffen.jahnke@eu.panasonic.com>
Currently, the sdhc_card_busy function is unimplemented in the
SDHC SPI-driver. This causes some functions which rely on f_sync(),
such as fs_close(), to fail as it will timeout the busy-check. This PR
implements sdhc_card_busy by checking if the MISO-line is kept high to
check if the SD-card is idle (not busy).
Solves https://github.com/zephyrproject-rtos/zephyr/issues/49982
Signed-off-by: Ivan Herrera Olivares <ivan.herreraolivares@uantwerpen.be>
In test_all_instances(), if ARRAY_SIZE(devices) is 0, the test is not
performed. At this time, the test result should be TC_FAIL, instead of
TC_PASS. A zassert is needed to filter this case.
Fixes: #45647
Signed-off-by: Hu Zhenyu <zhenyu.hu@intel.com>
1. enable timer5 on dts
2. Replace all BTMR_Type with struct btmr_regs, to make it compatiable
on both mec 15 and 17
3. As MEC15 and MEC17 have different ways to access the register, use
"#if defined" to access counter_cfg->girq_id on different board.
Signed-off-by: Hu Zhenyu <zhenyu.hu@intel.com>
Ensure that the FIFO of each endpoint is initialized during endpoint
configuration, to prevent a NULL FIFO from being encountered during the
first call to usb_dc_ep_write() for a given endpoint.
Signed-off-by: Nick Kraus <nick@nckraus.com>
Updated the document with the correct west build command,
and done some restructuring as well.
Signed-off-by: Rajkumar Kanagaraj <rajkumar.kanagaraj@linaro.org>
Add the flash channel support by implementing the controller attached
flash sharing APIs, including flash_read, flash_write, and flash_erase.
For flash_read, the max data payload the module can support is 64 bytes
in one transaction.
For flash_write, the max data payload the module can support is 16
bytes in one transaction.
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
Signed-off-by: Jun Lin <CHLin56@nuvoton.com>
In normal operation the clock for peripheral devices is derived from
the PLL clock.
During sleep, the xmc4xxx can switch its system clock source (f_sys)
from the PLL clock to an f_ofi clock. Switching to the f_ofi clock
is the default behaviour which breaks UART comms.
Use the PLL clock source during sleep instead to fix the issue.
Signed-off-by: Andriy Gelman <andriy.gelman@gmail.com>
When periodic advertising with chaining is re-enabled after
changing interval or just re-enabled then the chain PDUs
where not duplicated causing the LLL to assert detecting the
presence of aux pointer but no linked chain PDUs.
Signed-off-by: Vinayak Kariappa Chettimada <vich@nordicsemi.no>
DT node "st,stm32f105-pll2-clock" already exists but was not actually used
and PLL2 was not being configured.
PLL2 is available on STM32F105/F107 and should be turned off after turning
off PLL and turned on before turning on PLL again since PLL2 can be
used as a source for PLL. Source for PLL2 is always HSE.
Signed-off-by: Pierre-Emmanuel Novac <piernov@piernov.org>
The CONFIG_LOG_BACKEND_FORMAT_TIMESTAMP cannot be selected unless one of
the enumerated backends is selected. Add the ADSP_MTRACE backend to the
list, so timestamp formatting can be selected when only this backend is
enabled in the build.
Signed-off-by: Kai Vehmanen <kai.vehmanen@linux.intel.com>
Synch up to the mcu-tools/mcuboot SHA:
4030aac5944e5105f45bfcb02b7e0065810a8aeb
- Switched zephyr port from using FLASH_AREA_ macros to FIXED_PARTITION_
macros
- Made flash_map_backend.h compatible with a C++ compiler
- Enabled watchdog feed by default
- Allowed to get the flash write alignment basing on the zephyr,flash
DT chosen node property
Signed-off-by: Andrzej Puzdrowski <andrzej.puzdrowski@nordicsemi.no>
When building with CONFIG_SCHED_CPU_MASK_PIN_ONLY=y, CPU mask
is fixed and cannot be changed while thread is running.
The current code asserts if thread state is anything but PREPARED.
We do however have interface like k_work_queue_start() where a thread is
started as part of the queue start. To allow user to set the pinned CPU
for the work queue thread, it needs to be possible to suspend the
thread, set the mask, and then call k_thread_resume(). This seems to be
a valid sequence, so relax the assert check to reflect this.
Signed-off-by: Kai Vehmanen <kai.vehmanen@linux.intel.com>
Fixes an issue with outgoing mcumgr frames that are larger than the
transport MTU size whereby they would wrongly be split up into multiple
frames with multiple start frame headers, which affected SMP over
console transports.
Signed-off-by: Jamie McCrae <jamie.mccrae@nordicsemi.no>
Align backtrace output with the style used in rest of the codespace.
This makes it more convenient to compare the backtrace to e.g. objdump
output.
Signed-off-by: Kai Vehmanen <kai.vehmanen@linux.intel.com>
Note on dropping of zst parameter from zephyr_smp_transport_out_fn
callback type definition.
Signed-off-by: Dominik Ermel <dominik.ermel@nordicsemi.no>
`IS_ARRAY_ELEMENT(array, ptr)` behaves like `PART_OF_ARRAY()`
except that it checks that `ptr` is aligned to an array-element
boundary.
`ARRAY_INDEX(array, ptr)` returns the index of `ptr`, where
`ptr` is aligned to an array-element boundary.
`ARRAY_INDEX_FLOOR(array, ptr)` returns the index of `ptr`,
where `ptr` does not need to be aligned to an array-element
boundary.
If `CONFIG_ASSERT=y`, then `ARRAY_INDEX()` and
`ARRAY_INDEX_FLOOR()` will trigger an assertion for invalid
`ptr`.
Signed-off-by: Christopher Friedt <cfriedt@fb.com>
Add support to at86rf212[b] sub-giga devices. This work enables use of
pages 0, 2 and 5 in accordance with IEEE-802.15.4/2003/2006/2011. The
proprietary speeds can be object of future work.
Note: It is recommended that user define a power table for better
performance, low emissions and to save power. A reference power table
can be found in the datasheet and should be used for tests only and
not on a final product.
Signed-off-by: Gerson Fernando Budke <nandojve@gmail.com>
The current version of power table is hardcoded in the driver which is a
problem when use devices in production. This change remove all hardcode
from driver and reimplement the feature to allow people create a table
which is defined in devicetree. The big advantage is that each board can
define their own table based on lab tests and allows use of FEM devices
inclusive.
Signed-off-by: Gerson Fernando Budke <nandojve@gmail.com>
Allow using log_output without the logging subsystem. It can be
used in the situation where external messages are processed.
Signed-off-by: Krzysztof Chruscinski <krzysztof.chruscinski@nordicsemi.no>
The current stm32l562_dk_ns has no flash partitions defined. This add
flash partitions following partition sizes that are compatible with
the TF-M platform defined at flash_layout.h and removes the redundant
overlays board files.
Signed-off-by: Gerson Fernando Budke <gerson.budke@ossystems.com.br>
The lib/transport directory has been moved up, directly under the
subsys/mgmt/mcumgr, and all transport files have been moved to
that directory.
Signed-off-by: Dominik Ermel <dominik.ermel@nordicsemi.no>
fvp_base_revc_2xaemv8a supports up to 2 clusters and 8 cores, each
cluster has 4 cores.
Due to zephyr supports up to 4 cores, for now, I add another 3 cores,
they all belong to cluster0.
Signed-off-by: Huifeng Zhang <Huifeng.Zhang@arm.com>
On GICv3, when we send an IPI interrupt, aff3, aff2 and aff1 should
be assigned a value corespond to a PE for which interrupt will be
generated. target_list only corresponds to aff0.
On real hardware, aff3, aff2, aff1 and aff0 should be treated as a
whole to determine a PE.
Signed-off-by: Huifeng Zhang <Huifeng.Zhang@arm.com>
In old way, gic_rdists[cpu] is calculated via MPIDR_TO_CORE(), but in
real hardware, MPIDR_TO_CORE() isn't a value increment from 0 one by
one, and that will lead gic_rdists[cpu] to point to a wrong address.
GICv3 provides the register GICR_TYPER[1] and it has a field named
Affinity_Value. This field can help to determine where gic_rdists[cpu]
should point.
Signed-off-by: Huifeng Zhang <Huifeng.Zhang@arm.com>
Some reg size in fvp-aemv8r.dtsi isn't correct. This commit is used to
fix it.
- gic, the correct reg size is 0x10000 and 0x200000.
- uart0-3, the correct reg size is 0x10000.
Signed-off-by: Huifeng Zhang <Huifeng.Zhang@arm.com>
VMPIDR_EL2 is assigned the value returned by EL2 reads of MPIDR_EL1
MPIDR_EL1 is the register holding the Multiprocessor ID which is to
identify different cores. Because of the virtualization requirements
for AArch64, MPIDR_EL1 should be virtualized (the different virtualized
cores can run on the same physical core). Thus the value of MPIDR_EL1
should be switched when the VM is switched. Setting the VMPIDR_EL2 is
the way to change the value returned by EL1 reads of MPIDR_EL1. Even
without virtualization, we still need to set VMPIDR_EL2 during booting
at EL2 or EL3. Otherwise, all cores' IDs are zero at the EL1 stage
which will break the SMP system.
Signed-off-by: Huifeng Zhang <Huifeng.Zhang@arm.com>
As the TF-A was integrated into zephyr as a module. This adds necessary
CMake scripts to load BL1 and FIP binary built from TF-A.
Signed-off-by: Huifeng Zhang <Huifeng.Zhang@arm.com>
