QSPI doesn't have a different length expectation than normal SPI, so
introducing a new name for an existing name is unnecessary. Also
replace the constant with the actual buffer size where appropriate, in
somebody changes the the buffer definition.
Signed-off-by: Peter Bigot <peter.bigot@nordicsemi.no>
Kconfig allowed selecting any bit in the status register as the QE
bit, and defaulted it to 6. Devices need not require a QE bit at all,
and where JESD216 defines QE bit location the only place in first SR
byte that it can be is bit 6. Further, the code unconditionally wrote
the value 0x40 without respecting configuration of other bits. Some
of those bits control write protection of block-protected areas and
should not be changed.
Remove the Kconfig, instead using the jedec,jesd216-controlled
devicetree property. Allow the driver to recognize whether or not
setting the bit is required, and when it is only use bit 6. Only
update if the setting does not match the configuration.
Signed-off-by: Peter Bigot <peter.bigot@nordicsemi.no>
The interface used to send commands supports only a command followed
by 8 bytes of data transfer. Reject attempts to do more, as the
result will be a successful transfer of only the first 8 bytes.
Signed-off-by: Peter Bigot <peter.bigot@nordicsemi.no>
Not all special commands require that a write-enable be issued first.
Allow the caller to decide.
Signed-off-by: Peter Bigot <peter.bigot@nordicsemi.no>
DW16 provides information on mechanisms to enter and exit 4-Byte
address modes, returning the device to reset state, and how to
manipulate the values in the first status register.
Signed-off-by: Peter Bigot <peter.bigot@nordicsemi.no>
DW15 provides information on entry and exit from QSPI modes. In
particular, it specifies whether and how the status register must be
updated for this feature.
Add a JESD216 devicetree property for the Quad Enable Requirements
value.
Signed-off-by: Peter Bigot <peter.bigot@nordicsemi.no>
The folder name of a Zephyr module is also used as its module name
when integrating it into the build system.
This means that a Zephyr module, BAR, located in:
<workspace>/modules/foo
|--- zephyr
|--- CMakeLists.txt
|--- Kconfig
will be referred to as FOO in the build system, that is:
ZEPHYR_FOO_MODULE_DIR==<workspace>/modules/foo
ZEPHYR_FOO_CMAKE_DIR==<workspace>/modules/foo/zephyr
The `name` field allows the module to specify its module name,
independent of its location like:
<workspace>/modules/foo/zephyr/module.yml
```
name: bar
build:
cmake: zephyr
```
will instead be referred to as BAR in the build system, that is:
ZEPHYR_BAR_MODULE_DIR==<workspace>/modules/foo
ZEPHYR_BAR_CMAKE_DIR==<workspace>/modules/foo/zephyr
This allows for greater flexibility of relocating Zephyr modules in
other folders and at the same time be guaranteed that other modules
depending on `ZEPHYR_BAR_MODULE_DIR` is still working.
If `name` field is not specified in `module.yml`, then the existing
behavior of using the folder name will be used.
Signed-off-by: Torsten Rasmussen <Torsten.Rasmussen@nordicsemi.no>
When using Slim Bootloader the UART configuration isn't quite the same
as with the UEFI BIOS. In particular, UART2 is hidden in PCIe and is
instead accessible using a fixed MMIO address. Interrupts are also not
supported for this UART currently.
The simplest way to create builds against this special BIOS/bootloader
setup seems to be to create a new board variant/definition which lets
us provide a custom device tree overlay as well a dedicated Kconfig
default configuration.
Signed-off-by: Johan Hedberg <johan.hedberg@intel.com>
The bt-uart, uart-pipe and bt-mon-uart DT chosen values are all
Bluetooth specific. Since Bluetooth isn't supported on the ehl_crb
board currently just remove these.
Signed-off-by: Johan Hedberg <johan.hedberg@intel.com>
Add support for fixed MMIO (non-PCIe) UART devices for the early
serial. All we need to do is to detect if the device is on PCIe and
set the right register address define based on that.
Signed-off-by: Johan Hedberg <johan.hedberg@intel.com>
Add definitions for UART1/2 when they're accessible through fixed MMIO
addresses (instead of PCIe), and mark all UARTs not normally available
with the UEFI BIOS as "disabled".
Signed-off-by: Johan Hedberg <johan.hedberg@intel.com>
Instead of having a hard-coded maximum instance count, introduce a
Kconfig variable for it. The inclusion of the per-instance header
files is solved by having them chain-include each other with a
pre-processor condition that checks if the current header file is the
last one or not.
Signed-off-by: Johan Hedberg <johan.hedberg@intel.com>
The reg-shift support was quite broken in that the code only looked
for this property on instance 0. Now we support the property on any
node which might declare it.
Signed-off-by: Johan Hedberg <johan.hedberg@intel.com>
Take advantage of DT_INST_FOREACH_STATUS_OKAY() to look for DLF and
PCP properties on any matching nodes with "okay" status.
Signed-off-by: Johan Hedberg <johan.hedberg@intel.com>
Use a dependency block instead of specifying a UART_NS16550 dependency
for each individual opton. This doesn't save many lines right now, but
may do so once more options are added.
Signed-off-by: Johan Hedberg <johan.hedberg@intel.com>
The existing method of testing for any of the first four DT instances
having the pcie property feels a bit clumsy and will get more so when
support for more than four UARTs is added. A much more cleaner way to
do this (and more correct probably as well) is to list any PCIe-based
UART nodes under a pcie bus in the Device Tree hierarchy.
Signed-off-by: Johan Hedberg <johan.hedberg@intel.com>
Add a binding to represent a PCIe bus. This way PCIe devices can be
ordered under a parent PCIe bus object and make help of DT BUS macros
for conditional code.
Signed-off-by: Johan Hedberg <johan.hedberg@intel.com>
The definition of lock, k_spinlock type, that has been used to guard
variables holding statistical data for log_strdup has been missing
static modifier, which caused the lock structure to be reallocated
on stack each time an execution entered the block.
Signed-off-by: Dominik Ermel <dominik.ermel@nordicsemi.no>
Fix size of L2CAP disconnect request buffer pool which did not include
the size of the L2CAP signal header.
Regression from: 3346aa4d39
Signed-off-by: Joakim Andersson <joakim.andersson@nordicsemi.no>
Defined 625 and 1250 as context specific interval common to ULL and LLL.
Checked with bluetooth sanity checks.
Fixes#23314.
Signed-off-by: Nirosharn Amarasinghe <niag@demant.com>
Modify led_pwm sample in order to make it usable in device testing:
- Remove parenthesis from the logs as they prevent use of regex
- Add a harness_config multiline regex in order to enable verdict
generation
- Update README
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
This CL provided an example of how turns on the low-voltage level
detection feature in npcx series. It demonstrates enabling low-voltage
level detection of I2C1_0 SCL/SDA io-pads if the power rail of their PUs
is 1.8V.
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
Part of GPIO pads in npcx series support low-voltage (1.8V) level
detection. In order to introduce this feature, this CL adds a new
NPCX-specific controller property, lvol_io_pads, in devicetree file.
For example, here is devicetree fragment which turn on low-voltage
support of i2c1_0 port.
/ {
def_lvol_io_list {
compatible = "nuvoton,npcx-lvolctrl-def";
lvol_io_pads = <&lvol_io90 /* I2C1_SCL0 1.8V support */
&lvol_io87>; /* I2C1_SDA0 1,8V support */
};
};
Then these pads will turn on 1.8V level detection during initialization.
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
In bash a '&&' cannot follow directly after a '&'. So a task that is
run in the background should be enclosed in (curly) braces.
This:
```
west build -b qemu_x86 -d build/server samples/net/sockets/echo_server\
-- -DOVERLAY_CONFIG=overlay-qemu_802154.conf -DPCAP=capture.pcap
west build -t server -d build/server
```
works correctly after this fix.
Fixes#29793
Signed-off-by: Daniel Noom <ggatw@outlook.com>
Currently the following shields will thus be supported
waveshare_epaper_gdeh0154a07
waveshare_epaper_gdeh0213b1
waveshare_epaper_gdeh0213b72
waveshare_epaper_gdeh029a1
Signed-off-by: Kim Bøndergaard <kim@fam-boendergaard.dk>
Signed-off-by: Kim Bøndergaard <kibo@prevas.dk>
Add initial implementation of the uart async api
for stm32 mcus. This uses the dma controller
in normal mode for reception. In addition, to detect
reception of bytes we enable the idle line detection
interrupt.
Signed-off-by: Shlomi Vaknin <shlomi.39sd@gmail.com>
Signed-off-by: Jun Li <jun.r.li@intel.com>
Signed-off-by: Giancarlo Stasi <giancarlo.stasi.co@gmail.com>
This commit adds the asynchronous UART API testing support on the
nucleo_l4r5zi board.
The usart3 module is used as the secondary loop-back UART, which is
required to run this test.
Signed-off-by: Shlomi Vaknin <shlomi.39sd@gmail.com>
After finish transmitting some bytes might be in the
peripheral receive register, since the transmition
is still happening after reception disabled.
This patch ensures that the peripheral has no
bytes in its internal state.
Signed-off-by: Shlomi Vaknin <shlomi.39sd@gmail.com>
Some proprietary protocols that reuse the Bluetooth LLCP logic requires
that the CPR interval has a valid range that differs from the Bluetooth
specification defined.
Vendor must implement the function (ull_vendor.h)
uint16_t ull_conn_interval_min_get(struct ll_conn *conn)
that returns the valid limit for the given connection.
Signed-off-by: Thomas Ebert Hansen <thoh@oticon.com>
Firmware implementing the PSCI functions described in ARM document
number ARM DEN 0022A ("Power State Coordination Interface System
Software on ARM processors") can be used by Zephyr to initiate various
CPU-centric power operations.
It is needed for virtualization, it is used to coordinate OSes and
hypervisors and it provides the functions used for SMP bring-up such as
CPU_ON and CPU_OFF.
A new PSCI driver is introduced to setup a proper subsystem used to
communicate with the PSCI firmware, implementing the basic operations:
get_version, cpu_on, cpu_off and affinity_info.
The current implementation only supports PSCI 0.2 and PSCI 1.0
The PSCI conduit (SMC or HVC) is setup reading the corresponding
property in the DTS node.
Signed-off-by: Carlo Caione <ccaione@baylibre.com>
This commit introduces MODULE_EXT_ROOT which allows CMake and Kconfig
glue code to be placed outside of the Zephyr module repository.
This allows for placing glue code in Zephyr, but also allows users to
specify custom MODULE_EXT_ROOTs for glue code using either
`-DMODULE_EXT_ROOT` or `zephyr/module.yml` with
`build:settings:module_ext_root` settings.
MODULE_EXT_ROOT' is a list of directories, similar to other roots such
as BOARD_ROOT, DTS_ROOT, etc.
The Zephyr repo folder ${ZEPHYR_BASE} is always to the MODULE_EXT_ROOT
list as lowest priority.
For each MODULE_EXT_ROOT, the file
`<module_ext_root>/modules/modules.cmake` will be processed.
In Zephyr repo, the folder `modules/<module>/` contains CMakeLists.txt
and Kconfig glue code for the Zephyr module.
A Zephyr module can specify that CMakeLists.txt and Kconfig glue code is
placed in an external module root by specifying:
```
build:
cmake-ext: True
kconfig-ext: True
```
It is still possible to place the CMakeLists.txt and Kconfig files
directly in the Zephyr module using the existing:
```
build:
cmake: <path>
kconfig: <file>
```.
Signed-off-by: Torsten Rasmussen <Torsten.Rasmussen@nordicsemi.no>
register_event always returns 0, so the conditional will
always take the first branch and code in the else part
is never reached.
Fixes#31282
Signed-off-by: Ningx Zhao <ningx.zhao@intel.com>
Move iis2dlpc trigger pulse configurations from Kconfigs to Device Tree.
Moreover the dts properties have been renamed as 'tap', which sounds a
better name to immediately catch the feature behind it. Since tap
threshold cannot be zero, this value (which is the default in dts
binding) is used to enable/disable the device feature per each axis.
The event can be generated on INT1 only.
Signed-off-by: Armando Visconti <armando.visconti@st.com>
Simplify the switch case on trigger types (SENSOR_TRIG_DRDY and
SENSOR_TRIG_TAP) inside iis2dlpc_enable_int().
Signed-off-by: Armando Visconti <armando.visconti@st.com>
The IIS2DLPC drdy interrupt can be routed to either INT1 or
INT2 pin. Currently the selection is done by Kconfig configuration.
This commit is instead moving it into Device Tree as 'drdy-int'.
Signed-off-by: Armando Visconti <armando.visconti@st.com>
