Commit graph

56,286 commits

Author SHA1 Message Date
Peter Bigot
ee7c9f7fe8 libc: minimal: add INTn_C macros to stdint.h
Macros like INT64_C(x) convert x to a constant integral expression,
i.e. one that can be used in preprocessor code.  Implement wrappers
that use the GNUC intrinsics to perform the translation.

Signed-off-by: Peter Bigot <peter.bigot@nordicsemi.no>
2021-01-21 14:50:01 -05:00
Peter Bigot
5fd15c3038 tests: c_lib: fix include files
zephyr/types.h does not belong as a dependency for testing a C library
implementation of stdint.  Use the toolchain file directly.

Signed-off-by: Peter Bigot <peter.bigot@nordicsemi.no>
2021-01-21 14:50:01 -05:00
Enjia Mai
dd792ee11b tests: common: fix kernel.common test case build fail in intel_adsp_cavs
Fix kernel.common and kernel.common test cases fail due to build error
in platform intel_adsp_cavs15, 18, 20, 25.

Signed-off-by: Enjia Mai <enjiax.mai@intel.com>
2021-01-21 14:47:31 -05:00
Robert Lubos
075445b811 drivers: ieee802154_nrf5: Allocate net_pkt from correct pool
The driver allocated packet from the TX pool on its RX path. Fix this
by using a correct allocator function.

Signed-off-by: Robert Lubos <robert.lubos@nordicsemi.no>
2021-01-21 21:27:14 +02:00
Artur Lipowski
6871b61203 api: remove unnecessary parentheses in DEVICE_NAME_GET.
Get rid of compilation warnings caused by additional parentheses.

Signed-off-by: Artur Lipowski <Artur.Lipowski@hidglobal.com>
2021-01-21 11:29:07 -06:00
Gerard Marull-Paretas
5bc936e59e dts: arm: st: f0: fix timer 1 interrupt names
Timer 1 has two interrupts on STM32F0: TIM1_BRK_UP_TRG_COM_IRQn (13) and
TIM1_CC_IRQn (14). "brk" interrupt name does not reflect all the events
supported by the interrupt, so it has been renamed to "brk_up_trg_com".
On all other series except G0 timer 1 has a specific interrupt for each
event, so in such case "brk" is just fine.

Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
2021-01-21 17:33:23 +01:00
Gerson Fernando Budke
d86a0a74b7 boards: arm: cy8ckit_062_wifi_bt: m0: Add LED and switch
Add LED and switch DTS information.  Port P0 received the NVIC line 20
on Cortex-M0+ cpu.  This way, SW_0 switch can be connected as external
interrupt source for both m0 and m4 cpus.

Signed-off-by: Gerson Fernando Budke <gerson.budke@atl-electronics.com>
2021-01-21 17:33:11 +01:00
Gerson Fernando Budke
3027ebe952 boards: arm: cy8ckit_062_ble: m0: Add LED and switch
Add LED and switch DTS information.  Port P0 received the NVIC line 20
on Cortex-M0+ cpu.  This way, SW_0 switch can be connected as external
interrupt source for both m0 and m4 cpus.

Signed-off-by: Gerson Fernando Budke <gerson.budke@atl-electronics.com>
2021-01-21 17:33:11 +01:00
Gerson Fernando Budke
84d6a78ad1 drivers: gpio: Add Cypress PSoC-6 gpio driver
Introduce PSoC-6 GPIO support.

Signed-off-by: Gerson Fernando Budke <gerson.budke@atl-electronics.com>
2021-01-21 17:33:11 +01:00
Rohit Gujarathi
6910725ad9 drivers: display: Added Sharp memory display drivers.
Added support for sharp memory displays of the series
LS0XX.

Signed-off-by: Rohit Gujarathi <gujju.rohit@gmail.com>
2021-01-21 17:26:37 +01:00
Rohit Gujarathi
e892e09ad1 shields: display: Added LS013B7DH03 display shield.
Added sharp memory display LS013B7DH03 shield

Signed-off-by: Rohit Gujarathi <gujju.rohit@gmail.com>
2021-01-21 17:26:37 +01:00
Rohit Gujarathi
f023df581f drivers: display: Added support for restricted update.
Added support for restricted updating of monochrome
displays.

Signed-off-by: Rohit Gujarathi <gujju.rohit@gmail.com>
2021-01-21 17:26:37 +01:00
Peter Bigot
e0fd918bbd tests: i2c_slave_api: make dual role support optional
Not all I2C controllers that support dual roles allow a controller to
be used in both modes without reconfiguration: for some, registering a
slave device prevents use in master mode.  Refactor so that dual-role
operation is opt-in, and select it for the ST devices currently in the
allow list.

Signed-off-by: Peter Bigot <peter.bigot@nordicsemi.no>
2021-01-21 09:27:35 -06:00
Peter Bigot
787a5bc90c tests: i2c_slave_api: rework diagnostic output
Reduce the verbosity of the I2C log messages; we don't need to see
every transaction by default.

In the application replace use of the log infrastructure with TCPRINT,
and remove some messages that don't seem to be necessary.

Signed-off-by: Peter Bigot <peter.bigot@nordicsemi.no>
2021-01-21 09:27:35 -06:00
Marcin Niestroj
a471e55da0 drivers: wifi: esp: always request MRU bytes with AT+CIPRECVDATA
ESP chip send number of available RX data using
+IPD=<sock>,<avail_bytes> command. This exact number (truncated to MRU)
was used to read data with AT+CIPRECVDATA=<sock>,<num_of_bytes>.

Use always MRU when sending AT+CIPRECVDATA=<sock>,<mru> request. When
there are less bytes available, then +CIPRECVDATA will just return less
bytes, which is fine for the driver.

There are two advantages to this new behavior:
 * there is no need to follow how many bytes were notified by +IPD
   message, thus reducing implementation size,
 * when data is constantly received by ESP chip, then the last number of
   bytes notified by +IPD is no longer up-to-date when sending a
   AT+CIPRECVDATA; always requesting MRU number of bytes allows to
   always receive maximum currently available number of bytes buffered
   by ESP chip.

Signed-off-by: Marcin Niestroj <m.niestroj@grinn-global.com>
2021-01-21 15:43:47 +02:00
Marcin Niestroj
831a5f0e55 drivers: wifi: esp: rely on +IPD after each +CIPRECVDATA
Dump of communication between ESP chip and Zephyr shows that
+IPD:<sock>,<bytes_avail> is always received after +CIPRECVDATA. This
means that we don't need to update sock->bytes_avail in esp_workq
thread. Additionally there is no need to schedule next AT+CIPRECVDATA
request, as that will be done by +IPD handler anyway.

Relying on +IPD to be received after each +CIPRECVDATA (as long as there
is some more data to be received) allows to simplify operations on
sock->bytes_avail. From now on only esp_rx thread will update its value
and schedule AT+CIPRECVDATA in esp_workq thread. Then in
sock->bytes_avail will be treated as "readonly" in esp_workq
thread. This allows to prevent race condition when both esp_rx and
esp_workq threads could potentially update value of sock->bytes_avail
value at the same time.

<sock>,CLOSED message is received always after retrieving all data from
ESP chip (using AT+CIPRECVDATA), so there is no need to check whether
there are more bytes to be received before marking socket as closed in
Zephyr driver.

Signed-off-by: Marcin Niestroj <m.niestroj@grinn-global.com>
2021-01-21 15:43:47 +02:00
Andrei Emeltchenko
73bf31f028 edac: Remove magic numbers
Use proper defines instead of magic numbers.

Signed-off-by: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
2021-01-21 08:34:07 -05:00
Andrei Emeltchenko
abe6cb9428 edac: Add DTS bindings for IBECC
Add bindings for EDAC/IBECC. At the moment we can pass BDF and Vendor
ID.

Signed-off-by: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
2021-01-21 08:34:07 -05:00
Andrei Emeltchenko
e18379c474 edac: doc: Include EDAC API to Zephyr API Reference
Include EDAC API to generated Zephyr API Reference.

Signed-off-by: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
2021-01-21 08:34:07 -05:00
Andrei Emeltchenko
311732a0a0 edac: Replace DEVICE_AND_API_INIT with DEVICE_DEFINE
Since DEVICE_AND_API_INIT was recently deprecated replace with correct
version.

Signed-off-by: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
2021-01-21 08:34:07 -05:00
Andrei Emeltchenko
f4582b9478 edac: Add error data information to callback parameter
Add extra error data information to callback parameter. Add tests for
testing the data provided.

Signed-off-by: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
2021-01-21 08:34:07 -05:00
Andrei Emeltchenko
ae25a9926c edac: Remove extra logging
Remove unneeded extra logging.

Signed-off-by: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
2021-01-21 08:34:07 -05:00
Andrei Emeltchenko
064c9fe40f edac: Use helpers to read / write IBECC registers
Use helpers ibecc_{read,write}_reg{32,64}.

Signed-off-by: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
2021-01-21 08:34:07 -05:00
Andrei Emeltchenko
2dc413aa74 edac: Split EDAC set ctrl to set error_type and error_trigger
Split setting EDAC IBECC ctrl to setting error_type and
error_trigger to make it easier for other platforms.

Signed-off-by: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
2021-01-21 08:34:07 -05:00
Andrei Emeltchenko
f80628ba96 edac: Generalize EDAC API
Replace addr with param1 and addr_mask with param2 for get / set types
of functions. Those names are more general and allow to implement
error injections for other platforms.

Signed-off-by: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
2021-01-21 08:34:07 -05:00
Andrei Emeltchenko
61409a6d2f CODEOWNERS: Adding drivers/edac owner
Adding myself to the list for drivers/edac.

Signed-off-by: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
2021-01-21 08:34:07 -05:00
Andrei Emeltchenko
e33e5a7b57 edac: tests: Include sample.subsys.edac only for ehl_crb
Fixes twister build.

Signed-off-by: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
2021-01-21 08:34:07 -05:00
Andrei Emeltchenko
297d2eeb48 samples: edac: Add EDAC shell sample application
Add EDAC shell application demonstrating EDAC API usage. Can be used
for verification of the functionality with error injection mechanism.
Sample is also included in the twister tests.

Signed-off-by: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
2021-01-21 08:34:07 -05:00
Andrei Emeltchenko
5f06dbaebe edac: tests: Add injection API test
Add test injecting error and getting correct notification about EDAC
error. Since we have logging enabled in the exception handler it does
not work with LOG_MINIMAL.

Signed-off-by: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
2021-01-21 08:34:07 -05:00
Andrei Emeltchenko
f2cd5f753f edac: tests: Add testing EDAC IBECC API
Add testing EDAC API, can be run on device ehl_crb.

Signed-off-by: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
2021-01-21 08:34:07 -05:00
Andrei Emeltchenko
f7f2dd85be edac: shell: Add EDAC shell
Add EDAC shell module which would be included in the EDAC sample.

Signed-off-by: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
2021-01-21 08:34:07 -05:00
Andrei Emeltchenko
2b30d04eef edac: ibecc: Add EDAC IBECC driver
Add In-Band ECC driver. Supported in ehl_crb board.

Signed-off-by: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
2021-01-21 08:34:07 -05:00
Andrei Emeltchenko
d4d278da0a edac: Add Zephyr EDAC configuration
Add Kconfig for EDAC.

Signed-off-by: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
2021-01-21 08:34:07 -05:00
Andrei Emeltchenko
6caec8cb4f edac: Add EDAC API
Add Error Detection And Correction (EDAC) API.

Signed-off-by: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
2021-01-21 08:34:07 -05:00
Gerson Fernando Budke
f93ee9508b soc: arm: cypress: psoc6: Add Cortex-M0+ int mux support
PSoC-6 SoC needs that user define the nvic interrupt number to bind
with the peripheral interrupt line for the Cortex-M0+ CPU.  It uses
a multiplex before any NVIC interrupt line.  The interrupt vector is
selected using interrupt-parent property with the intmux_chN number
reference.

Note: The PSoC-6 SoC allows that both CPUs receive the same interrupt.
A tipical use is GPIO interrupt handle and user is responsable to
define interrupt line, priority and take care of enable same peripheral
instance on both CPUs only when appropriated.

Signed-off-by: Gerson Fernando Budke <gerson.budke@atl-electronics.com>
2021-01-20 17:54:09 -06:00
Gerson Fernando Budke
04773afffd dts: arm: cypress: psoc6: Drop nvic reference
The psoc6.dtsi file declare a reference to nvic.  Since it was proper
defined at psoc6_cm0/4.dtsi files this entry is redundant.  Drop the
useless entry.

Signed-off-by: Gerson Fernando Budke <gerson.budke@atl-electronics.com>
2021-01-20 17:54:09 -06:00
Gerson Fernando Budke
2ad591f756 soc: arm: cypress: psoc6: Update soc.h includes
Update <soc.h> include files.  This removes the unnecessary
<kernel_includes.h> file.  In addition, add <sys/util.h> to
expose macros and <devicetree.h> following general standards.

Signed-off-by: Gerson Fernando Budke <gerson.budke@atl-electronics.com>
2021-01-20 17:54:09 -06:00
Dawid Niedzwiecki
6ec4ff22e3 emul: Add an emulator for the eSPI Host
This emulator pretends a generic eSPI Host. It supports basic virtual
wires and port80 operations.

There are functions to trigger actions on the host side e.g. for
setting a virtual wire from the host to the eSPI slave, use
emul_espi_host_send_vw. It will prepare data and set a proper event
on the slave side which will trigger callback (if there is any).

Signed-off-by: Dawid Niedzwiecki <dn@semihalf.com>
2021-01-20 17:49:19 -05:00
Dawid Niedzwiecki
d1948dc164 emul: espi: Add support for eSPI emulators
Add an emulation controller which routes eSPI traffic to attached
emulators depending on the selected chip(mostly host).
This allows drivers for eSPI peripherals to be tested on systems
that don't have that peripheral attached, with the emulator handling
the eSPI traffic.

Signed-off-by: Dawid Niedzwiecki <dn@semihalf.com>
2021-01-20 17:49:19 -05:00
Daniel Leung
ff720cd9b3 x86: enable soft float support for Zephyr SDK
This adds the correct compiler and linker flags to
support software floating point operations. The flags
need to be added to TOOLCHAIN_*_FLAGS for GCC to find
the correct library (when calling GCC with
--print-libgcc-file-name).

Note that software floating point needs to be turned
on for Newlib. This is due to Newlib having floating
point numbers in its various printf() functions which
results in floating point instructions being emitted
from toolchain. These instructions are placed very
early in the functions which results in them being
executed even though the format string contains
no floating point conversions. Without using CONFIG_FPU
to enable hardware floating point support, any calls to
printf() like functions will result in exceptions
complaining FPU is not available. Although forcing
CONFIG_FPU=y with newlib is an option, and because
the OS doesn't know which threads would call these
printf() functions, Zephyr has to assume all threads
are using FPU and thus incurring performance penalty as
every context switching now needs to save FPU registers.
A compromise here is to use soft float instead. Newlib
with soft float enabled does not have floating point
instructions and yet can still support its printf()
like functions.

Signed-off-by: Daniel Leung <daniel.leung@intel.com>
2021-01-20 16:45:31 -05:00
Anas Nashif
d0dd2ac5d3 samples: cmsis_rtos_v2: increase stack
Need more stack for some platforms and architectures.

Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2021-01-20 16:45:31 -05:00
Anas Nashif
8b3d9e7285 sparc: do not set cmsis api Kconfigs
Those should be set by applications, not architectures.

Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2021-01-20 16:45:31 -05:00
Anas Nashif
13fdb9e73d doc: update docs with 0.12.1 SDK
Update documentation with new SDK version.

Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2021-01-20 16:45:31 -05:00
Anas Nashif
be00feb6eb ci: switch to 0.12.1 SDK
Move to new SDK.

Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2021-01-20 16:45:31 -05:00
Peter Bigot
08f4ce4efb samples: boards: nrf: add clock_skew
Provide a demonstration of using the timeutil skew infrastructure to
measure the relative error of the two clock sources on Nordic boards.

Signed-off-by: Peter Bigot <peter.bigot@nordicsemi.no>
2021-01-20 16:38:56 -05:00
Peter Bigot
7b3dc4856a doc: add a section for timeutil APIs
Describe the role of these APIs, key concepts that they depend on, and
expose the low-level API.

Signed-off-by: Peter Bigot <peter.bigot@nordicsemi.no>
2021-01-20 16:38:56 -05:00
Peter A. Bigot
f6d7595d4e lib/timeutil: add utilities to manage local/reference clock alignment
Provide data structures to capture a timestamp in two different
clocks, monitor the drift between those clocks, and using a base
instant with estimated drift convert between the clocks.

This provides the core technology to convert between system uptime and
an external continuous time scale like TAI (UTC without applying leap
seconds).

Signed-off-by: Peter A. Bigot <pab@pabigot.com>
2021-01-20 16:38:56 -05:00
Spoorthy Priya Yerabolu
513b9f598f zefi.py: Use cross compiler while building zephyr
Currently, zefi.py takes host GCC OBJCOPY as
default. Fixing the script to use CMAKE_C_COMPILER
and CMAKE_OBJCOPY.

Fixes: #27047

Signed-off-by: Spoorthy Priya Yerabolu <spoorthy.priya.yerabolu@intel.com>
2021-01-20 16:38:12 -05:00
Klaus H. Sorensen
8216e320b6 canbus: canopen: program: read flash in 32 byte chunks
Add routine to calculate crc of flash region. Read 32 bytes at a time
from flash instead of 4 bytes, for a significant speed up of the flash
image crc calculation.

Signed-off-by: Klaus H. Sorensen <khso@vestas.com>
2021-01-20 14:18:03 -06:00
Klaus H. Sorensen
cb24e3c22e canbus: canopen: program: unlock can od during flash access
The callback function canopen_odf_1f56 is called with the can od lock
held. Release the lock while performing time consuming flash reading and
crc calculations, and reacquire the lock before returning from the
function.

Signed-off-by: Klaus H. Sorensen <khso@vestas.com>
2021-01-20 14:18:03 -06:00