More to be added, but for now show that we can map more
anonymous memory than we physically have, and that reading/
writing to it works as expected.
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
Show we can measure free memory properly and map a page of
anonymous memory, which has been zeroed and is writable.
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
This will enable testing of the implementation until the
critical set of pages is identified and known to the
kernel.
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
All arch_ APIs and macros are implemented, and the page fault
handling code will call into the core kernel.
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
Implement runtime APIs for pinning, paging in, and evicting
memory, as well as the page fault hook called from architecture
code.
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
Backing stores and eviction algorithms will be included here.
Exactly one must be chosen, with a default option to leave
the implementation to the application.
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
Architecture layer hooks for demand paging. See
doxygen for these API definitions for more details.
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
Page tables created at build time may not include the
gperf data at the very end of RAM. Ensure this is mapped
properly at runtime to work around this.
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
Pre-allocation of paging structures is now required, such that
no allocations are ever needed when mapping memory.
Instantiation of new memory domains may still require allocations
unless a common page table is used.
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
We no longer use a page pool to draw memory pages when doing
memory map operations. We now preallocate the entire virtual
address space so no allocations are ever necessary when mapping
memory.
We still need memory to clone page tables, but this is now
expressed by a new Kconfig X86_MAX_ADDITIONAL_MEM_DOMAINS
which has much clearer semantics than specifying the number
of pages in the pool.
The default address space size is now 8MB, but this can be
tuned by the application.
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
Just tell the kernel that RAM starts 1MB in, period.
Better simulation of a low-memory microcontroller as
we're not managing a very large number of page frames
we'll never use.
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
Previously, newlib claimed all free physical memory in the
system.
Now, the kernel manages this, allowing for memory to be
used via k_mem_map() calls.
Establish an upper bound to how much newlib will try to
claim on system startup, instead of trying to take all
of it, allowing other parts of the system to also map
anonymous memory.
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
We now draw heap memory from an anonymous memory mapping
instead of a hard-coded region past the kernel image,
which is no longer mapped by default.
Some readability cleanups were made to a particuarly
horrible set of nested ifdefs. A few types were adjusted.
sbrk()'s count argument is an intptr_t, not an int.
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
All RAM may not be mapped. Check the mapping for the main kernel
image and the locore if it exists.
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
A more comprehensive solution would use E820 enumeration, but we
are unlikely to ever care that much, as we intend to use demand
paging on microcontrollers and not PC-like hardware. This is
really to just prevent QEMU from crashing.
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
Allows applications to increase the data space available to Zephyr
via anonymous memory mappings. Loosely based on mmap().
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
Add linker symbols corresponding to the start and end of the
mapped Zephyr image. This is not used by the ARM arch yet, but
is required to compile the core kernel MMU code.
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
We will use this to map the kernel instead of all RAM.
The end of the kernel is always page-aligned, regardless
of CONFIG_SRAM_REGION_PERMISSIONS as it must be mapped.
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
These are needed on MMU systems and define where the kernel
image resides in virtual memory at boot so that it may be
memory-mapped.
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
This is only needed if the base address of SRAM doesn't
have the same alignment as the base address of the virtual
address space.
Fix the calculations on X86 where this is the case.
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
Coded PHY is only enabled by default if the application is using
BT_HCI_RAW.
Coded PHY is not needed in most applications.
By disabling Coded PHY, most applications will:
* Get smaller in terms of flash and ram usage
* Not get vurnerable to devices trying to switch to Coded and
thereby increasing power consumption.
Signed-off-by: Rubin Gerritsen <rubin.gerritsen@nordicsemi.no>
Use TX FIFO level interrupt if available in hardware. It matches the
Zephyr UART API and avoids "bootstrapping" which is needed when using
the TX edge interrupt ("TI"). TX FIFO has room for up to 32 characters
and will typically reduce the number of interrupts.
Details:
APBUART can be synthesized with or without support for TX/RX FIFO.
Edge interrupts which fire when TX holding register changes and RX data
available are always available, independent of the FIFO configuration.
If FIFO is made available at synthesis time, two additional interrupts
become available: TX FIFO half-empty and RX FIFO half-full. These
are level interrupts.
Signed-off-by: Martin Åberg <martin.aberg@gaisler.com>
This commit aligns the GRLIB APBUART driver with the Zephyr UART API
and fixes an issue where TX interrupt could previously be lost. It
was typically seen during interactive operation in the Zephyr shell.
There is an expectation in the Zephyr UART API that TX ready (i.e. TX
buffer space available) interrupt is a level interrupt, i.e. always
active while there's TX buffer space available. In particular, there's
an expectation that after uart_irq_tx_enable(), the TX interrupt will
immediately fire (assuming free TX buffer space is available).
The APBUART "Transmitter interrupt (CTRL_TI)" does not directly fulfill
this expectation because it is edge triggered and fires when the TX
holding register moves from being non-empty to empty. The solution
is to "bootstrap" interrupt processing by calling user-defined ISR
in irq_tx_enable().
This fix is similar to commit 49bb163756 ("drivers: serial:
uart_cmsdk_apb: Fix interrupt-driven operation").
Signed-off-by: Martin Åberg <martin.aberg@gaisler.com>
Refactor the output of device list to use standard API to retrieve the
list of devices, and to always display a status rather than hiding
disabled/failed devices.
Add API to associate a distinct identifier with any "device" that does
not have a name.
Where a device has requires dependencies display the devices on which
it depends.
Signed-off-by: Peter Bigot <peter.bigot@nordicsemi.no>
Following the idiom used for system calls, add script support to read
the initial application binary to identify which devices are defined,
and to use their offset in the device array as their unique handle
rather than the externally-defined ordinal from devicetree. The
device dependency arrays are updated to use these handles.
Signed-off-by: Peter Bigot <peter.bigot@nordicsemi.no>
Generate arrays of dependency information for each device. If a
device definition is being constructed from devicetree these come from
the devicetree dependency information. Additional dependencies may be
passed through using the DT_ macros.
Define flag values for device handles so we can partition the
dependency array into distinct sets, which include things it requires,
things it supports (may not be needed), and child nodes (not
implemented, may not be needed).
Signed-off-by: Peter Bigot <peter.bigot@nordicsemi.no>
These need to be gpio controllers and have the necessary specifier
properties for use in gpio specifiers.
Signed-off-by: Peter Bigot <peter.bigot@nordicsemi.no>
Add board support files for mimxrt1024_evk, the development board for
i.MXRT1024(CM7) SoC.
- Add pinmux, dts, doc.
- Code can be loaded to SRAM.
- Tested samples: hello_world, philosophers, synchronization,
basic/blinky, and basic/button.
Signed-off-by: Lucien Zhao <lucien.zhao@nxp.com>
