Add support for the FVP Base RevC 2xAEMv8A board to be emulated using
the same FVP. For now the virtual platform is only exposing one core and
the basic set of peripherals (GICv3, ARM arch timer, PL011, etc...).
INFO - Total complete: 256/ 256 100% skipped: 933, failed: 0
Signed-off-by: Carlo Caione <ccaione@baylibre.com>
Refactor best practices from the API refactoring issue and integrate
them into the existing documentation.
Signed-off-by: Peter Bigot <peter.bigot@nordicsemi.no>
Reference the helper macro used to obtain the containing context
structure from a work item pointer within a work handler. Also
document the proper way to do this for delayable work items.
Signed-off-by: Peter Bigot <peter.bigot@nordicsemi.no>
Point out that this macro can be used to avoid the need to initialize
a work item. This is still of limited use since it can't statically
initialize a work item within another structure.
Signed-off-by: Peter Bigot <peter.bigot@nordicsemi.no>
Use queued uniformly when referring to items that are in a work queue,
rather than "pending" which includes items that are scheduled or
running.
Signed-off-by: Peter Bigot <peter.bigot@nordicsemi.no>
The return value is documented to be true if the work was pending, but
the implementation returned true only if the work was actually running
(i.e. the caller had to wait). It should also return true if
scheduled or submitted work was cancelled.
Note that this means the return value cannot be used to determine
whether the call slept.
Signed-off-by: Peter Bigot <peter.bigot@nordicsemi.no>
The NATIVE_TASK macro uses macros from the toolchain header.
Instead of relaying on the header to be included by somebody else,
include it explicity here.
Signed-off-by: Alberto Escolar Piedras <alpi@oticon.com>
Initializing a work item from its handler will destroy the content of
the kernel structures used to process the work item. This can lead to a
system crash for example when the delayed work is being rescheduled when
the previous run is already queued for processing but not yet executed.
Fix this by initializing the work item once during trickle timer
creation and moving the logic, previously achieved by switching the work
handler, into the new work handler.
Signed-off-by: Robert Lubos <robert.lubos@nordicsemi.no>
Do not configure this as a test, this will change footprint drastically
and will skew results and tracking.
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Introduce revision for cy8ckit_062_ble board. Revision 0.0.0 represent
the original board schematic which connects Arduino header signals to
PSoC-6 KitProg. The revision 1.0.0 should be used after board rework
to access other serial ports and full Arduino headers.
Signed-off-by: Gerson Fernando Budke <gerson.budke@atl-electronics.com>
Add pinctrl and interrupt information for both cores. The uart-6 is
the default serial communication on the kit connected to m0 core. It
uses SCB[6] and the NVIC line 21 as interrupt source on Cortex-M0+ cpu.
The line 21 is an arbitrary value and users can select any value. The
SCB[6] shares pins with Arduino headers D8/D9. It may be necessary an
USB serial converter to sample signals and enable Zephyr console on PC.
The uart-5 is the default serial communication port for m4. It is
connected to Arduino serial line. A HW rework may need to allow
Arduino header to be useful.
Signed-off-by: Gerson Fernando Budke <gerson.budke@atl-electronics.com>
Add pinctrl and interrupt information for both m0/4 cores. The uart-5
is the default serial communication on the kit and it is connected to
Cortex-M0+ cpu. It uses SCB[5] and the NVIC line 21 as interrupt
source on Cortex-M0+ cpu. The line 21 is an arbitrary value and users
can select any value. The SCB[5] shares pins with Arduino headers
D0/D1 and it is wired with the on-board USB Serial converter. This
means, if use wants use an external shield it must rework the board.
The uart-6 is the default serial communication for Cortex-M4 cpu, which
uses SCB[6].
Signed-off-by: Gerson Fernando Budke <gerson.budke@atl-electronics.com>
Current Cypress PSoC-6 serial driver only works using polling mode.
Add serial driver interrupt routines to allow use of interrupts.
Signed-off-by: Gerson Fernando Budke <gerson.budke@atl-electronics.com>
The current serial driver uses hard code configuration. Rework driver
to use pinctrl and enable full configuration from device tree.
Signed-off-by: Gerson Fernando Budke <gerson.budke@atl-electronics.com>
Add pinctrl-0 properties for configuration of UART, I2C, SPI, FTM,
DAC, ADC, ACMP, and PWT peripherals. These settings are based on what
is defined in the board/pinmux.c file.
Signed-off-by: Henrik Brix Andersen <hebad@vestas.com>
Add a function that uses the JESD216 SFDP BFP DW16 Enter 4-Byte
Addressing parameter to put the device into 4-byte addressing mode if
one of the entry modes that's supported by the driver is available on
the device.
Perform the transition if SFDP data is provided (either by devicetree
or at runtime), or if a special devicetree property provides the entry
mode descriptor.
Signed-off-by: Peter Bigot <peter.bigot@nordicsemi.no>
Support both 24-bit and 32-bit address values when constructing the
device command. Note that some commands require 24-bit address
regardless of mode, and some require 32-bit addresses regardless of
mode, so provide command-specific overrides of a generic (but not yet
configurable) default address size.
With this we no longer need a special interface for READ_SFDP which
uses a 24-bit address but with a wait state introduced by clocking out
a fifth command byte.
Signed-off-by: Peter Bigot <peter.bigot@nordicsemi.no>
This driver abstracts most access through a generic function that
supports both read and write with and without address components in
the command. Rework this so that instead of distinct arguments
specifying the combination of features there's a flag set that will
allow more combinations to be specified.
Signed-off-by: Peter Bigot <peter.bigot@nordicsemi.no>
Fixes#29915.
Implements the memory layout and MPU configuration for Ethernet buffers
for STM32H7 controllers as recommended by ST. 16 KB of SRAM3 are
are reserved for this. The first 256 B are for the RX/TX descriptors and
configured as strongly ordered, shareable memory. The rest is for RX/TX
buffers and configured as non cacheable memory. This configuration is
automatically applied for H7 chips if the SRAM3 memory is enabled in the
device tree.
Signed-off-by: Mario Jaun <mario.jaun@gmail.com>
When building and running the rpmsg_service sample on MPS2 AN521
use the mps2_an521_remote target to build the Zephyr image
for the remote core.
Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
When building and running the openamp sample on MPS2 AN521,
use the mps2_an521_remote target to build the Zephyr image
for the remote core.
Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
We do not need to have dependencies any more on !OPENAMP
for BUILD_WITH_TFM in the mps2 an521 target, because we
now have different targets for the non-secure version of
the board and the remote core.
Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
Add a new target for MPS2 AN521, called mps2_an521_remote.
This target is used in dual image MPS2 AN521 builds, for
the 'remote' target. It is indentical to mps2_an521_nonsecure,
except for the fact that it does not enable TrustZone-M and
it does not set the security domain to Non-Secure.
Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
Kconfig symbol is used in hal_stm32 module to define Cube HAL
symbol HSE_VALUE (cf hal_stm32/stm32cube/CMakeLists.txt).
Due to this specific usage, this symbol should be kept. As a
consequence it could not be replaced by dts equivalent but we can
use dts to configure it.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Optionally configure Kconfig SYS_CLOCK_HW_CYCLES_PER_SEC using
clock-frequency provided by dt if sysclk node is enabled
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Provided nodes reflect the clock tree of each series.
Clock nodes are disabled by default but populated with default
start up configuration. Main reason is the we don't want to
impact boards using Kconfig based clock configuration for now.
Exception to these rules:
- syslck: Default enabled, clock frequency and clock source not
provided
- pll: clock source not provided
This is made on purpose so that errors are triggered if parameters
essential to the board configuration are not provided.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
To allow transition to device tree based clock configuration on
stm32 targets, rework clock_control driver to use intermediate
STM32_ macros initially defined as the equivalent Kconfig macros
for now.
Propagate the change in all code using these macros.
The reason to introduce these new macros instead of configuring
Kconfig flags using dt kconfigfunctions is that we'll need
to be able to inform users that Kconfig flags are deprecated
once the whole family conversion is done, to encourage
out of tree users to adopt this new configuration scheme.
Note: For now STM32H7 series and code is excluded.
This is the same for some series specific code such as
PLL mul/div for L0/L1 and XTRE prescaler on F1 series.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
The timestamp is no longer depending on TX/RX time config
options so move it to separate settings.
Signed-off-by: Jukka Rissanen <jukka.rissanen@linux.intel.com>
This value is used to measure the RX/TX statistics. The previous
use of the timestamp field did not work in RX path as the timestamp
value could be overwritten by the driver if gPTP timestamping
is enabled. So to fix the RX statistics, use a separate field
for the create time.
Signed-off-by: Jukka Rissanen <jukka.rissanen@linux.intel.com>
If user enables CONFIG_USERSPACE, then at least one TX or RX thread
is needed to isolate the application from the kernel space components.
Signed-off-by: Jukka Rissanen <jukka.rissanen@linux.intel.com>
