Set the default behaviour of the networking subsystem so that
no TX or RX threads are created. This will save RAM as there
is no need to allocate stack space for the RX/TX threads.
Also this will give small improvement to network packet latency
shown here:
* with 1 traffic class (1 TX and RX thread)
Avg TX net_pkt (42707) time 60 us [0->22->15->22=59 us]
Avg RX net_pkt (42697) time 36 us [0->10->3->12->7=32 us]
* with 0 traffic classes (no TX and RX threads)
Avg TX net_pkt (41608) time 42 us [0->21->20=41 us]
Avg RX net_pkt (41593) time 31 us [0->9->12->8=29 us]
In this qemu_x86 test run, 40k UDP packets was transferred between
echo-server and echo-client. In TX the speed increase was 30% and
in RX it was 14%.
Signed-off-by: Jukka Rissanen <jukka.rissanen@linux.intel.com>
For testing purposes, add simulated PTP clock device to e1000
Ethernet driver that is used in qemu_x86 board. The PTP clock
does nothing useful as there is no real hw behind this device.
We just emulate the clock in order to do some SO_TXTIME testing.
Signed-off-by: Jukka Rissanen <jukka.rissanen@linux.intel.com>
Set the net_pkt creation time just before the actual net_pkt
is allocated in order to get more accurate information for
statistics.
Signed-off-by: Jukka Rissanen <jukka.rissanen@linux.intel.com>
It is possible that user wants to access PTP clock but does
not need gPTP support. The networking txtime sample does exactly
this.
Signed-off-by: Jukka Rissanen <jukka.rissanen@linux.intel.com>
It is possible that user wants to access PTP clock but does
not need gPTP support. The networking txtime sample does exactly
this.
Signed-off-by: Jukka Rissanen <jukka.rissanen@linux.intel.com>
If user has set the priority of the sent net_pkt to highest
priority (NET_PRIORITY_CA) and enabled CONFIG_NET_TC_SKIP_FOR_HIGH_PRIO
option, then push that packet directly to driver instead of TX queue.
This will make the TX sending latency smaller for the high priority
packet. This is not enabled by default.
Signed-off-by: Jukka Rissanen <jukka.rissanen@linux.intel.com>
This application shows how to use SO_TXTIME option, which can be
used to specify the time when the network packet should be sent
out by the network device driver.
Signed-off-by: Jukka Rissanen <jukka.rissanen@linux.intel.com>
Tests are designed to run over the DUMMY interface but when run on
hardware, net_if_get_default() can return the actual hardware
interface.
Fixes: #31969
Signed-off-by: David Leach <david.leach@nxp.com>
If there is a UARTE receive error (e.g. framing or break), the RXTO
event may never come. Check error event too, to avoid an infinite loop.
Signed-off-by: Jim Paris <jim@jim.sh>
This CL adds a override mechanism for pwm module's input clock source
assignment. If the 'clock-bus' property exists, the NPCX_DT_PROP_ENUM_OR
macro function will return an enum upper token value. Otherwise, it
expands to default value in 'clocks' property.
For example, if the users want to select LFCLK as pwm0's input clock,
ths node can be overridden by adding 'clock-bus' property with an enum
string, "NPCX_CLOCK_BUS_LFCLK".
&pwm0 {
status = "okay";
clock-bus = "NPCX_CLOCK_BUS_LFCLK";
};
Signed-off-by: Keith Short <keithshort@google.com>
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
It's easier and safer to parse json file rather than extract
total size from stdout
Now the .json file has two keys:
{
"symbols": {
"children": [
...
],
"identifier": ":",
"name": "root",
"size": 2220
},
"total_size": 34272
}
Signed-off-by: Jingru Wang <jingru@synopsys.com>
i2s1 is not present in all stm32f4 series. So moving the i2s1 node
from the top level stm32f4 dtsi file to the stm32fxx specific dtsi
files. Also in stm32f429zi, the sequence starts from i2s2, this commit
helps in having the right channel number.
Signed-off-by: Krishna Mohan Dani <krishnamohan.d@hcl.com>
Replace all existing deprecated API with the recommended alternative.
Fixes#34102
Signed-off-by: Peter Bigot <peter.bigot@nordicsemi.no>
Signed-off-by: Gerson Fernando Budke <nandojve@gmail.com>
Add dts nodes for onboard devices that have drivers in zerphyr src
- Add PWM for all leds
- Add LSM303AGR sensor node
- Add LSM303DLHC node for PCB rev B
- Create PCB rev B overlay and make PCB rev D default.
Signed-off-by: Sahaj Sarup <sahaj.sarup@linaro.org>
After the introduction of usart1 the kernel/genisr_table test could
no longer build, due to an interrupt conflict.
Adopt the TEST_NUM_IRQS to resolve the conflict.
Signed-off-by: Thomas Stranger <thomas.stranger@outlook.com>
Adds nucleo_g071rb board to the uart_async_api test.
Therefore additionally add usart1 in board definitions.
Signed-off-by: Thomas Stranger <thomas.stranger@outlook.com>
Fix stm32_dma_is_irq_active not checking the IRQ status(IsEnabled) for
active interrupts.
While the transfer-complete, half-transfer comp. and transfer-error
is_XX_irq_active() functions check for IRQ status (IsEnabled),
ORing the result with dma_stm32_is_gi_active() overrides the
status check as gi is always 1 in case any of these flags is active.
Related to commit 96c92ed93f.
Signed-off-by: Thomas Stranger <thomas.stranger@outlook.com>
Enables dma test cases loop_transfer and chan_blen_transfer
on stm32g03116_disco, nucleo_g071rb and nucleo_g0b1re.
Signed-off-by: Thomas Stranger <thomas.stranger@outlook.com>
Use LL_DMAMUX_CHANNEL_x defines instead of DMAMUX_CSR_SOF7x to check
if corresponding LL_DMAMUX_IsActiveFlag_SOx and LL_DMAMUX_ClearFlag_SOx
inline functions exist and should be added to func_ll_is_active_so[]
and func_ll_clear_so[].
The HAL of some socs uses the same flag to decide which registers exist
on a specific soc. And the same defines are used for table_ll_channel[]
initializations.
This is necessary because DMAMUX_CSR_SOF5 and DMAMUX_CSR_SOF6 were
wrongly added in the HALs soc header file for some stm32g0 socs,
therefore without this change some stm32g0 socs couldn't compile.
Signed-off-by: Thomas Stranger <thomas.stranger@outlook.com>
Update the existing driver to support STM32G0 series.
It enables the DMA_STM32_SHARED_IRQS flag for g0 series, such that
all interrupts are handled in a shared isr to avoid irq conflicts.
The shared isr is extended to be able to handle irqs from more than one
dma instance.
Furthermore the config_irq function of instance 1, which connects to the
irqs, was reworked to avoid irq conflicts when 2 dma instances on
stm32f0, or stm32g0 are enabled:
While dma1 has one exclusive irq for channel 1, and one irq for dma1
channels 2 and 3, all other channels share the same irq.
Therefore it is currently not possible to enable dma2 without enabling
dma1 at the same time, without getting an build errror due to an irq
conflict.
Signed-off-by: Thomas Stranger <thomas.stranger@outlook.com>
Not all STM32 Series can enable a dedicated clock for dmamux.
In stm32g0 series for example the clock is enabled automatically
as long as either DMA1 or DMA2 is enabled.
This commit changes dmamux driver to cope with socs that don't have
defined a clocks property. Therefore it moves the config(and data)
struct into the c file to be able to use DT_INST_NODE_HAS_PROP macro.
Signed-off-by: Thomas Stranger <thomas.stranger@outlook.com>
STM32G0 is supported by the st,stm32-dma-v2 driver.
This commit adds dma1 and dmamux dts bindings
for stm32g03x, stm32g05x and stm32g07x.
For stm32g0bx additionally dma2 is added.
Signed-off-by: Thomas Stranger <thomas.stranger@outlook.com>
In case of ARC MWDT toolchain and C++ support enabled the Zephyr .init*
section conflicts with .init* sections derived from toolchain libs.
Let's add 'z_' prefix to Zephyr .init* section (and therefore .device
section as they share the same macros) to make Zephyr section name
unique.
Signed-off-by: Evgeniy Paltsev <PaltsevEvgeniy@gmail.com>
It has been seen that when net backend is enabled stack usage
is around 1080. Setting 1152 as the default.
Signed-off-by: Krzysztof Chruscinski <krzysztof.chruscinski@nordicsemi.no>
Kconfig symbol NFCT_PINS_AS_GPIOS may be defined for all
Nordic nRF SoCs that have the NFCT hardware, so we move
the option definition in nRF common Kconfig file. Also,
we correct the help text to reflect that nRF52 series DKs
and nRF5340 DK have different pins for NFC.
Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
The configuration is based on
the f303k6 and the ST reference manual.
I had successfully tested the following sample code:
blinky
blink_led (uses TIM2_CH2 on PB3)
hello_world
Signed-off-by: Sebastian Schwabe <sebastian-schwabe@gmx.de>
This commit adds the soc config for the STM32F031k6 and STM32F031X6.
Add the STM32F031k6 as choice to the Kconfig.soc.
Signed-off-by: Sebastian Schwabe <sebastian-schwabe@gmx.de>
Exit latency time should never be greater than the residency time.
Just add an assert in case the policy does not properly handle it.
Signed-off-by: Flavio Ceolin <flavio.ceolin@intel.com>
pm_power_state_force no longer requires the idle thread to run.
Just removing the following k_sleep for two reasons, first it is
not necessary, second it tests that pm_power_state_force works
as it should.
Signed-off-by: Flavio Ceolin <flavio.ceolin@intel.com>
pm_power_state_force no longer requires the idle thread to run. Just
removing the following k_sleep for two reasons, first it is not
necessary, second it tests that pm_power_state_force works as it
should.
Signed-off-by: Flavio Ceolin <flavio.ceolin@intel.com>
Set the timeout to expire "exit_latency_us" earlier to the CPU be
capable of honor the next scheduled event.
Signed-off-by: Flavio Ceolin <flavio.ceolin@intel.com>
Using more realistic values to avoid confusion and make it clear the
distinction between min-residency-us and other idle properties like
exit-latency-us.
Signed-off-by: Flavio Ceolin <flavio.ceolin@intel.com>
Exit latency is the maximum time required by a CPU to transition from
a specific idle state to active state. This information is going to be
used to properly configure the wake up event in order to the system be
able to execute the next scheduled task.
Signed-off-by: Flavio Ceolin <flavio.ceolin@intel.com>
Moves the callback structure for VOCS to the register function
which is renamed from init, as there's no reason to register
the callbacks separately.
Signed-off-by: Emil Gydesen <emil.gydesen@nordicsemi.no>
In SMP, MPID is mybe not equal to cpu logic ID, so can't
use MPID to get rdist base address from gic_rdists[], this
patch get logic ID from arch_curr_cpu()->id, and
find current CPU's rdist base address from:
gic_rdists[cpu_logic_id]
Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.com>
