Commit graph

142 commits

Author SHA1 Message Date
Daniel Leung
fe10897f70 uart: ns16550: simplify DLF and PCP related macros
This simplifies DLF and PCP enabling devicetree macros with
DT_ANY_INST_HAS_PROP_STATUS_OKAY() instead of the complicated
ones.

Also, this moves the macro to initialize struct elements into
the struct initializer itself. This makes it clearer on which
element is being initialized directly inside the struct
initializer instead of having to do mental macro trampoline
to find the correct macro.

Signed-off-by: Daniel Leung <daniel.leung@intel.com>
2023-09-26 12:03:04 +02:00
Daniel Leung
2899df629f uart: ns16550: remove unused forward declaration
Remove the unused forward declaration of the driver API struct.

Signed-off-by: Daniel Leung <daniel.leung@intel.com>
2023-09-26 12:03:04 +02:00
Girisha Dengi
f0ac2347da drivers: serial: Add optional reset line for uart_ns16550
If the optional hardware reset line is available, this change
will use that reset line to assert the uart module and bring
it out of reset state to use.

Signed-off-by: Girisha Dengi <girisha.dengi@intel.com>
2023-07-25 16:58:01 +00:00
Daniel Leung
20021abf0a serial: ns16550: check return of clock_control_get_rate()
This adds a check of the return of clock_control_get_rate(),
and returns error in uart_configure() if unsuccessful in
getting clock rate.

Fixes #60478

Signed-off-by: Daniel Leung <daniel.leung@intel.com>
2023-07-24 09:07:11 +00:00
L Lakshmanan
24759511f4 drivers: uart: Add support for UART_NS16550 TI K3 variant
TI K3 family of SoCs requires an extended set of registers to operate.
Extended functionality of the current driver to support the variant.

Signed-off-by: L Lakshmanan <l-lakshmanan@ti.com>
2023-07-14 09:37:44 +02:00
Najumon B.A
b4ed6c4300 drivers: serial: driver init level based on parent node
Boot level based on parent node (PCI or no PCI device). Some platforms the
PCI bus driver depends on ACPI sub system to retrieve platform information
such as interrupt routing information. But ACPI sub system currently
support only post kernel and hence such platforms the UART driver instance
init should be invoked only post kernel in case parent node is PCI.

Signed-off-by: Najumon B.A <najumon.ba@intel.com>
2023-07-08 09:00:03 +03:00
Daniel Leung
d88840a8aa Revert "drivers: serial: ns16550: Add support for Async APIs"
This reverts commit 2d03aaf99f.

The async API for NS16550 is incomplete. We are near the next
release so it is better to revert it for now, and a proper
correct implementation can be done before next-next release.

Relates to #57103

Signed-off-by: Daniel Leung <daniel.leung@intel.com>
2023-06-13 06:59:33 -04:00
Anisetti Avinash Krishna
79f2b5471c drivers: serial: ns16550: Fixed a bug related to shell failure
Updated boot priority to PRE_KERNEL_1 for all instances
and removed dependency on PCIe. As shell is not working
in a situation where console is using a UART instance
under PCIe and boot priority set to POST_KERNEL.

Signed-off-by: Anisetti Avinash Krishna <anisetti.avinash.krishna@intel.com>
2023-04-13 20:50:41 -04:00
Anisetti Avinash Krishna
2d03aaf99f drivers: serial: ns16550: Add support for Async APIs
Added support for async APIs for ns16550. This will be
enabled by kconfig CONFIG_UART_ASYNC_API.

Signed-off-by: Anisetti Avinash Krishna <anisetti.avinash.krishna@intel.com>
2023-04-06 07:50:42 +00:00
Anisetti Avinash Krishna
26133e995d drivers: serial: ns16550: Enable simultaneous support of IO, MMIO and PCIe
Enabled simultaneous support by adding a DTS variable named “io-mapped”.
There are 3 possibilities through instance in dtsi file.
Under PCIe, PCIe ns16550.
Under soc and has a variable io-mapped, legacy(IO mapped).
Under soc and don’t have a variable io-mapped, MMIO mapped.
Simultaneous access can be enabled by a Kconfig.
For PCIe instances UART initialization should be done post-kernel as it
depends on PCIe initialization.

Co-authored-by: Najumon BA <najumon.ba@intel.com>
Signed-off-by: Anisetti Avinash Krishna <anisetti.avinash.krishna@intel.com>
2023-03-30 09:43:29 -04:00
Anisetti Avinash Krishna
00991e4720 drivers: serial: ns16550: Moved PCIe probe to init function
Moved PCIe probe from configure function to init function
because whenever uart_configure api is called MMIO address
is getting updated.

Signed-off-by: Anisetti Avinash Krishna <anisetti.avinash.krishna@intel.com>
2023-03-21 18:10:12 +00:00
Anisetti Avinash Krishna
712dab4f04 drivers: serial: ns16550: Fixed set_baud_rate usage in line ctrl set
Added pclk parameter to set_baud_rate function in line_ctrl_set api
which was missed during update of set_baud_rate function definition
update.

Signed-off-by: Anisetti Avinash Krishna <anisetti.avinash.krishna@intel.com>
2023-03-21 18:10:12 +00:00
Grant Ramsay
9df37fff79 drivers: serial: Add pinctrl support to the NS16550 driver
This enables configuring pins for the UART

Signed-off-by: Grant Ramsay <gramsay@enphaseenergy.com>
2023-03-02 13:50:06 +01:00
Johan Hedberg
fcfff0633e drivers: uart_ns16550: Convert to use runtime PCIe BDF lookup
Convert the ns16550 driver to use the new centralized runtime BDF lookup
of PCIe devices.

Signed-off-by: Johan Hedberg <johan.hedberg@intel.com>
2022-11-16 11:18:43 +01:00
Daniel Leung
bbb2f8277a uart: ns16550: move command macro to public header
This moves the CMD_SET_DLF command macro to public header
so application can use it without weird include path to
include the "private" header file under drivers/serial.

Signed-off-by: Daniel Leung <daniel.leung@intel.com>
2022-11-10 22:40:21 -05:00
Henrik Brix Andersen
3c99a1e015 drivers: pcie: reintroduce support for I/O BARs
Reintroduce support for accessing I/O BARs which was removed in
43d84147d9.

Signed-off-by: Henrik Brix Andersen <henrik@brixandersen.dk>
2022-11-01 15:22:31 -04:00
Gerard Marull-Paretas
178bdc4afc include: add missing zephyr/irq.h include
Change automated searching for files using "IRQ_CONNECT()" API not
including <zephyr/irq.h>.

Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
2022-10-17 22:57:39 +09:00
Henrik Brix Andersen
9456eca5c0 drivers: serial: check if clock device is ready before accessing
Add check for device_is_ready() before accessing clock control devices.

Signed-off-by: Henrik Brix Andersen <hebad@vestas.com>
2022-08-09 17:16:16 +02:00
Teik Heng Chong
f551c29576 drivers: serial: Uart ns16550 get clock frequency from clock manager
This patch is to enhance the uart ns16550 driver to get clock frequency
from clock manager or devicetree if clock_frequency is defined.

Signed-off-by: Teik Heng Chong <teik.heng.chong@intel.com>
2022-07-05 15:38:54 +00:00
Gerard Marull-Paretas
985bdcd076 drivers: serial: ns16550: simplify reg-shift code
The driver supported getting register shift from Devicetree, from a
custom definition in SoC headers (fragile) or, it took a default value.
This change simplifies things by making reg-shift property required in
all instances.

Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
2022-06-15 16:59:02 -05:00
Gerard Marull-Paretas
4cafd8df7e drivers: serial: ns16550: remove redundant soc.h include
<soc.h> has been traditionally been used as a proxy to HAL headers,
register definitions, etc. Nowadays, <soc.h> is anarchy. It serves a
different purpose depending on the SoC. In some cases it includes HALs,
in some others it works as a header sink/proxy (for no good reason), as
a register definition when there's no HAL... To make things worse, it is
being included in code that is, in theory, non-SoC specific.

This patch is part of a series intended to improve the situation by
removing <soc.h> usage when not needed, and by eventually removing it.

Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
2022-06-05 14:48:40 +02:00
Gerard Marull-Paretas
92f488497f drivers: serial: ns16550: use MMIO device depending on Kconfig option
Add a new selectable Kconfig option to decide wether the device driver
is a MMIO device or not. Previous to this patch, the decision was maded
based on the existence of a definition in <soc.h>. The design was
fragile, as code compiled anyway if the definition was not present.

All platforms/boards that had the definition in <soc.h> select the
Kconfig option in their respective defconfig files.

Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
2022-06-05 14:48:40 +02:00
Dino Li
5a1c084447 driver/serial: ns16550: set NS16550 as default variant
This add UART_NS16550_VARIANT_16550 configuration inside the choice
of UART_NS16550_VARIANT_NS16750 and UART_NS16550_VARIANT_NS16950.
The configuration is enabled by default to make NS16550 device to get
correct FIFO size configuration (16 bytes).

fixes #45783

Signed-off-by: Dino Li <Dino.Li@ite.com.tw>
2022-05-27 11:55:31 -07:00
Esteban Valverde
797b6784bb drivers: serial: modify ns16550 to use extended FIFO
Cyclone V SoC FPGA supports 128Byte FIFO for UART communication,
this modification adds a feature to use 128byte FIFO serial UART

Signed-off-by: Esteban Valverde <esteban.valverde.vega@intel.com>
2022-05-10 13:29:47 -04:00
Gerard Marull-Paretas
fb60aab245 drivers: migrate includes to <zephyr/...>
In order to bring consistency in-tree, migrate all drivers to the new
prefix <zephyr/...>. Note that the conversion has been scripted, refer
to #45388 for more details.

Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
2022-05-06 19:58:21 +02:00
Carlo Caione
69b28bfd07 pm: policy: Consider substates for state lock functions
Extend the current pm_policy_state_lock_*() functions to support
substates.

Signed-off-by: Carlo Caione <ccaione@baylibre.com>
2022-04-28 16:32:23 +02:00
Gerard Marull-Paretas
5a71eeb35c pm: policy: move constraints to policy API
The pm_constraint_* APIs were effectively used by the policy manager
only. This patch renames the API to the policy namespace and makes its
naming more explicit:

- pm_constraint_set -> pm_policy_state_lock_get()
- pm_constraint_release -> pm_policy_state_lock_put()
- pm_constraint_get -> pm_policy_state_lock_is_active()

The reason for these changes is that constraints can be of many types:
allow/disallow states, impose latency requirements, etc. The new naming
also makes explicit that the API calls will influence the PM policy
behavior.

All drivers and documentation have been updated accordingly.

Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
2022-03-16 15:26:47 +01:00
Gerard Marull-Paretas
1674fec5b6 drivers: serial: drop DEV_DATA/DEV_CFG usage
Stop using redundant DEV_DATA/DEV_CFG macros and use dev->data and
dev->config instead.

Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
2022-01-19 18:16:02 +01:00
Daniel Leung
bff37a3a6c drivers: serial: remove @return doc for void functions
For functions returning nothing, there is no need to document
with @return, as Doxgen complains about "documented empty
return type of ...".

Signed-off-by: Daniel Leung <daniel.leung@intel.com>
2022-01-12 16:02:16 -05:00
Gerard Marull-Paretas
10fb5789ef drivers: serial: ns16550: use pm_state_cpu_get_all
Use pm_state_cpu_get_all to obtain CPU states instead of using extra ROM
duplicating existing information already holded by the PM subsystem.

Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
2022-01-11 10:46:20 +01:00
Tomasz Bursztyka
f7a2ff4f8d drivers: Fixing the 2 drivers for PCIe IRQ connection
Now these 2 drivers should be working properly in case of IRQ remapping.

Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
2022-01-07 10:47:27 -05:00
Gerard Marull-Paretas
5ab7d35e7c pm: state: PM_STATE_DT_ITEMS_LIST->PM_STATE_LIST_FROM_DT_CPU
Rename the PM_STATE_DT_ITEMS_LIST macro to PM_STATE_LIST_FROM_DT_CPU to
make its purpose more clear. Similar naming scheme is found e.g. in the
GPIO API.

Associated internal macros and docstrings have been adjusted, too.

Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
2021-12-04 12:33:57 -05:00
Tim Lin
f52ff1a79e drivers/serial: uart_ns16550: add power management constraint API
Instead of busy wait until completed transaction, the constraint set
is used before enabling tx interrupt to not allow system to enter
suspend when tx is transmitting.

Application defined policy should use the pm_constraint_get function
to check if given state is enabled and could be used.

TEST=Test on hayato board(soc:it8xxx2), the logs print normally before
system enters suspend.

Signed-off-by: Tim Lin <tim2.lin@ite.corp-partner.google.com>
2021-12-02 10:53:19 +01:00
Timo Teräs
1eb6831ddd drivers: uart_ns16550: Fix dts hw_flow_control mapping to config
DT_INST_NODE_HAS_PROP() returns true always since the boolean
tag is valid. Use DT_INST_PROP_OR() to get the real value.

Fixes: baecd7e55a drivers: uart_ns16550: Remove CMake-based templating
Signed-off-by: Timo Teräs <timo.teras@iki.fi>
2021-10-20 07:13:42 -04:00
Maureen Helm
ad1450510a drivers: serial: Refactor drivers to use shared init priority Kconfig
Refactors all of the serial drivers to use a shared driver class
initialization priority configuration, CONFIG_SERIAL_INIT_PRIORITY, to
allow configuring serial drivers separately from other devices. This is
similar to other driver classes like I2C and SPI.

The default is set to CONFIG_KERNEL_INIT_PRIORITY_DEVICE to preserve the
existing default initialization priority for most drivers. The one
exception is uart_lpc11u6x.c which previously used
CONFIG_KERNEL_INIT_PRIORITY_OBJECTS.

This change was motivated by an issue on the frdm_k64f board where the
serial driver was incorrectly initialized before the clock control
driver.

Signed-off-by: Maureen Helm <maureen.helm@intel.com>
2021-10-17 10:58:09 -04:00
Daniel Leung
ef0d955758 uart: ns16550: add workaround to re-enable interrupts in ISR
In some configurations (e.g. edge interrupt triggers),
an interruptible event occurs during ISR and the host interrupt
controller does not see the new event due to IIR is constantly
asserting interrupts. For example, the callback handles RX and
then TX. If another character comes in before end of TX processing
(TX interrupt still asserts while raising RX interrupt), the host
interrupt controller may not see this new event. So if needed,
the IER is being toggled to re-assert interrupts at the end of ISR
to nudge the host interrupt controller to fire the ISR again.

Signed-off-by: Daniel Leung <daniel.leung@intel.com>
2021-10-04 20:49:13 -04:00
Dawid Niedzwiecki
1031cfd51e drivers: serial: ns16550: fill full fifo
Put the maximum number of bytes into Tx FIFO in the fill_fifo routine
to reduce CPU usage.

Previously, the THRE bit was checked in a loop, but, according to doc -
"In the FIFO mode, it is set when the XMIT FIFO is empty, and is
cleared when at least one byte is written to XMIT FIFO.", so only one
byte was transferred every interrupt. That was generating a big amount
of interrupts, which consumes CPU time.

Signed-off-by: Dawid Niedzwiecki <dn@semihalf.com>
2021-09-28 20:10:00 -04:00
Dawid Niedzwiecki
3e696a0f84 drivers: serial: ns16550: fix uart initialization
Do not set DLAB bit in Line Control Register when the access to
the baud rate divisor registers is not needed.

Signed-off-by: Dawid Niedzwiecki <dn@semihalf.com>
2021-09-13 07:06:33 -04:00
Tomasz Bursztyka
f70ecc1099 drivers/pcie: Improve and fix MBAR retrieval depending on use cases
So far pcie_get_mbar() has been the only way to retrieve a MBAR. But
it's logic does not fit all uses cases as we will see further.
The meaning of its parameter "index" is not about BAR index but about
a valid Base Address count instead. It's an arbitrary way to index
MBARs unrelated to the actual BAR index.

While this has proven to be just the function we needed so far, this has
not been the case for MSI-X, which one (through BIR info) needs to
access the BAR by their actual index. Same as ivshmem in fact, though
that one did not generate any bug since it never has IO BARs nor 64bits
BARs (so far?).

So:

- renaming existing pcie_get_mbar() to pcie_probe_mbar(), which is a
  more relevant name as it indeed probes the BARs to find the nth valid
  one.
- Introducing a new pcie_get_mbar() which this time really asks for the
  BAR index.
- Applying the change where relevant. So all use pcie_probe_mbar() now
  but MSI-X and ivshmem.

Fixes #37444

Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
2021-08-20 06:30:20 -04:00
Daniel Leung
4e1692f85a serial: introduce CONFIG_UART_USE_RUNTIME_CONFIGURE
This kconfig option enables runtime configuration of UART
controllers. This allows application to call uart_configure()
to configure the UART controllers and calling uart_config_get()
to retrieve configuration. If this is disabled, UART controllers
rely on UART driver's initialization function to properly
configure the controller. The main use of this option is mainly
code size reduction.

Fixes #16231

Signed-off-by: Daniel Leung <daniel.leung@intel.com>
2021-06-07 12:09:01 +02:00
Gerard Marull-Paretas
a4081b66d8 drivers: serial: remove usage of device_pm_control_nop
device_pm_control_nop is now deprecated in favour of NULL.

Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
2021-04-28 12:25:39 -04:00
Johan Hedberg
9e9a990ba0 drivers: uart_ns16550: Fix naming for struct uart_ns16550_dev_data_t
Rename uart_ns16550_dev_data_t to uart_ns16550_dev_data since it's not a
typedef.

Signed-off-by: Johan Hedberg <johan.hedberg@intel.com>
2021-04-22 15:30:24 -05:00
Johan Hedberg
baecd7e55a drivers: uart_ns16550: Remove CMake-based templating
With some additional macro-magic we can remove the CMake-based header
file template feature, and instead take advantage of the usual
DT_INST_FOREACH_STATUS_OKAY() macro.

Signed-off-by: Johan Hedberg <johan.hedberg@intel.com>
2021-04-22 15:30:24 -05:00
Peng Li
e28b7e04e2 driver: serial: fixed the buffer underflow issue when clearing the port.
Set DLAB bit before reading RDR to avoid buffer underflow.

Signed-off-by: Peng Li <lipengit@gmail.com>
2021-04-15 17:19:12 +02:00
Johan Hedberg
4fa0a9b4b2 drivers: serial: ns16550: Remove hard-coded max instance count
Instead of having a hard-coded maximum instance count, introduce a
Kconfig variable for it. The inclusion of the per-instance header
files is solved by having them chain-include each other with a
pre-processor condition that checks if the current header file is the
last one or not.

Signed-off-by: Johan Hedberg <johan.hedberg@intel.com>
2021-01-18 15:45:58 -05:00
Johan Hedberg
048dcea54b drivers: serial: ns16550: Remove reg-shift instance count assumption
The reg-shift support was quite broken in that the code only looked
for this property on instance 0. Now we support the property on any
node which might declare it.

Signed-off-by: Johan Hedberg <johan.hedberg@intel.com>
2021-01-18 15:45:58 -05:00
Johan Hedberg
0cb118968d drivers: serial: ns16550: Remove DLF & PCP instance count assumptions
Take advantage of DT_INST_FOREACH_STATUS_OKAY() to look for DLF and
PCP properties on any matching nodes with "okay" status.

Signed-off-by: Johan Hedberg <johan.hedberg@intel.com>
2021-01-18 15:45:58 -05:00
Johan Hedberg
1d5d5fcf49 drivers: uart: ns16550: Move all PCIe-using nodes to a PCIe bus in DTS
The existing method of testing for any of the first four DT instances
having the pcie property feels a bit clumsy and will get more so when
support for more than four UARTs is added. A much more cleaner way to
do this (and more correct probably as well) is to list any PCIe-based
UART nodes under a pcie bus in the Device Tree hierarchy.

Signed-off-by: Johan Hedberg <johan.hedberg@intel.com>
2021-01-18 15:45:58 -05:00
Maximilian Bachmann
3c8e98cb39 drivers/pcie: Change pcie_get_mbar() to return size and flags
currently pcie_get_mbar only returns the physical address.
This changes the function to return the size of the mbar and
the flags (IO Bar vs MEM BAR).

Signed-off-by: Maximilian Bachmann <m.bachmann@acontis.com>
2020-11-20 09:36:22 +02:00
Tomasz Bursztyka
4dcfb5531c isr: Normalize usage of device instance through ISR
The goal of this patch is to replace the 'void *' parameter by 'struct
device *' if they use such variable or just 'const void *' on all
relevant ISRs

This will avoid not-so-nice const qualifier tweaks when device instances
will be constant.

Note that only the ISR passed to IRQ_CONNECT are of interest here.

In order to do so, the script fix_isr.py below is necessary:

from pathlib import Path
import subprocess
import pickle
import mmap
import sys
import re
import os

cocci_template = """
@r_fix_isr_0
@
type ret_type;
identifier P;
identifier D;
@@
-ret_type <!fn!>(void *P)
+ret_type <!fn!>(const struct device *P)
{
 ...
(
 const struct device *D = (const struct device *)P;
|
 const struct device *D = P;
)
 ...
}

@r_fix_isr_1
@
type ret_type;
identifier P;
identifier D;
@@
-ret_type <!fn!>(void *P)
+ret_type <!fn!>(const struct device *P)
{
 ...
 const struct device *D;
 ...
(
 D = (const struct device *)P;
|
 D = P;
)
 ...
}

@r_fix_isr_2
@
type ret_type;
identifier A;
@@
-ret_type <!fn!>(void *A)
+ret_type <!fn!>(const void *A)
{
 ...
}

@r_fix_isr_3
@
const struct device *D;
@@
-<!fn!>((void *)D);
+<!fn!>(D);

@r_fix_isr_4
@
type ret_type;
identifier D;
identifier P;
@@
-ret_type <!fn!>(const struct device *P)
+ret_type <!fn!>(const struct device *D)
{
 ...
(
-const struct device *D = (const struct device *)P;
|
-const struct device *D = P;
)
 ...
}

@r_fix_isr_5
@
type ret_type;
identifier D;
identifier P;
@@
-ret_type <!fn!>(const struct device *P)
+ret_type <!fn!>(const struct device *D)
{
 ...
-const struct device *D;
...
(
-D = (const struct device *)P;
|
-D = P;
)
 ...
}
"""

def find_isr(fn):
    db = []
    data = None
    start = 0

    try:
        with open(fn, 'r+') as f:
            data = str(mmap.mmap(f.fileno(), 0).read())
    except Exception as e:
        return db

    while True:
        isr = ""
        irq = data.find('IRQ_CONNECT', start)
        while irq > -1:
            p = 1
            arg = 1
            p_o = data.find('(', irq)
            if p_o < 0:
                irq = -1
                break;

            pos = p_o + 1

            while p > 0:
                if data[pos] == ')':
                    p -= 1
                elif data[pos] == '(':
                    p += 1
                elif data[pos] == ',' and p == 1:
                    arg += 1

                if arg == 3:
                    isr += data[pos]

                pos += 1

            isr = isr.strip(',\\n\\t ')
            if isr not in db and len(isr) > 0:
                db.append(isr)

            start = pos
            break

        if irq < 0:
            break

    return db

def patch_isr(fn, isr_list):
    if len(isr_list) <= 0:
        return

    for isr in isr_list:
        tmplt = cocci_template.replace('<!fn!>', isr)
        with open('/tmp/isr_fix.cocci', 'w') as f:
            f.write(tmplt)

        cmd = ['spatch', '--sp-file', '/tmp/isr_fix.cocci', '--in-place', fn]

        subprocess.run(cmd)

def process_files(path):
    if path.is_file() and path.suffix in ['.h', '.c']:
        p = str(path.parent) + '/' + path.name
        isr_list = find_isr(p)
        patch_isr(p, isr_list)
    elif path.is_dir():
        for p in path.iterdir():
            process_files(p)

if len(sys.argv) < 2:
    print("You need to provide a dir/file path")
    sys.exit(1)

process_files(Path(sys.argv[1]))

And is run: ./fix_isr.py <zephyr root directory>

Finally, some files needed manual fixes such.

Fixes #27399

Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
2020-09-02 13:48:13 +02:00