Add a name to the h4 rx thread.
It's useful to put a name on each thread for debugging, e.g., with the
shell's kernel threads command.
Signed-off-by: Pete Skeggs <peter.skeggs@nordicsemi.no>
Convert allowed_cmds to an array of atomic_t of size 1.
This makes it future proof in case more commands are added.
Possibly silences coverity false positives on array vs singleton usage.
Signed-off-by: Joakim Andersson <joakim.andersson@nordicsemi.no>
Fix some format warning in cfg_cli.c.
Fix use CID_VNAL as param when use vendor models.
This is a resubmission of PR (#30086)
Signed-off-by: Lingao Meng <menglingao@xiaomi.com>
Fixed some undesired or incorrect macros, which
can cause build error.
This is a resubmission of PR (#30086)
Signed-off-by: Lingao Meng <menglingao@xiaomi.com>
Correct format errors, such as oob action 2-octers
should use 0x%04x, and action in prov capalilities pdu
big-ending. When every call `bt_mesh_auth_method_set<*>`
should also clear auth value, otherwise will case confirm
failed.
Provisioner role expect peer public key should be sent
immediately, instead of requiring ACK. After all, ACK may
be lost, and the other device’s public key will be sent
over, and provisioning procedure will be failed..
This is a resubmission of PR (#30086)
Signed-off-by: Lingao Meng <menglingao@xiaomi.com>
Zero initialize the ch_handle in dma_pl330_configure().
The memset in dma_pl330_config_channel()is incorrect,
as the ch_handle is already populated with valid values and
the dma_pl330_config_channel() is overwriting with zeros.
Signed-off-by: Arjun Jyothi <arjun.jyothi@broadcom.com>
This sets the dts of dma for using the uart asynch api.
The stm32l475 has a dmamux with request 2 for Tx/Rx usart4
The Tx&Rx pins (PA0, PA1) of the usart4 are connected
on the disco_l475_iot1 board to pass the test.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
To remove the need of empty config files, the `board_check_revision()`
now accepts a list of valid revisions.
As example:
```
board_check_revision(
FORMAT MAJOR.MINOR.PATCH
VALID_REVISIONS 0.1.0 0.5.0 0.10.0
)
```
The code is still compatible with the `<board>_<revision>.conf` changes
so that if different revisions of a board has Kconfig differences, then
there is no need to also specify the list of valid revisions.
Signed-off-by: Torsten Rasmussen <Torsten.Rasmussen@nordicsemi.no>
AArch64 has support for PSCI. This is especially useful for SMP because
PSCI is used to power on the secordary cores.
When the PSCI driver was introduced in Zephyr it was designed to rely on
a very PSCI-centric subsystem / interface.
There are two kinds of problems with this choice:
1. PSCI is only defined for the non-secure world and it is designed to
boot CPU cores into non-secure state (that means that PSCI is only
supposed to work if Zephyr is running in non-secure state)
2. There can be other ways or standards used to start / stop a core
different from PSCI
This patch is trying to fix the original wrong assumption by making the
interface / subsystem a generic one, called 'pm_cpu_ops', and using PSCI
only as an actual driver that is a user of this new interface /
subsystem.
For now the new subsystem is only exposing two methods: cpu_on and
cpu_off, others will probably follow according to the needs.
Signed-off-by: Carlo Caione <ccaione@baylibre.com>
There is no strict reason to use assembly for the reset routine. Move as
much code as possible to C code using the proper helpers.
Signed-off-by: Carlo Caione <ccaione@baylibre.com>
Introduce C helpers for common assembly operations and preprocessor
constructors to create helper functions to read / write system
registers.
Signed-off-by: Carlo Caione <ccaione@baylibre.com>
The name for registers and bit-field in the cpu.h file is incoherent and
messy. Refactor the whole file using the proper suffixes for bits,
shifts and masks.
Signed-off-by: Carlo Caione <ccaione@baylibre.com>
The Semtech SX1272MB2DAS shield is populated with a SX1272 LoRa
transceiver. The base board must provide Arduino header pins
definitions.
Signed-off-by: Christian Taedcke <christian.taedcke@lemonbeat.com>
The cmd_write and cmd_ctunc have been opening/creating file for
read/write operation.
The commit changes cmd_write to open/create file for write only,
and cmd_trunc to only open file for write.
Signed-off-by: Dominik Ermel <dominik.ermel@nordicsemi.no>
The way these scripts looked for the current working directory
was not correct or reliable. With this change it should
work properly.
Signed-off-by: Alberto Escolar Piedras <alpi@oticon.com>
The README gives as example the command to build
the sample with west. The path of the sample as
stated does not exist. This fixes it to blinky_pwm.
Signed-off-by: Jennifer Williams <jennifer.m.williams@intel.com>
When instructed to flash the combined Secure and Non-Secure
binary, we need to modify the hex file used in west flash.
The combined binary is named tfm_merged.hex, regardless of
building with or without BL2.
Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
In nRF5340, instruct the build to flash, by default, the
combined Secure (TF-M) and Non-Secure (Zephyr) binaries
as a merged binary, using west flash, if we are building
in-tree tests.
Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
Introduce an option to instruct the build system
to flash the Non-Secure (Zephyr) firmware image
together with the TF-M (Secure) firmware image
as a single merged binary, instead of just flashing
the Non-Secure application.
Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
Add devicetree node representing the PCAL6408A I2C-based I/O expander
that is available in nRF9160 DK v0.14.0 or later.
Provide also .dtsi files that can be used in applications to simplify
switching to interfacing onboard LEDs and buttons through this expander
instead of SoC pins.
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
Use the multiple board revisions feature to provide support for the new
hardware possibilities available in nRF9160 DK starting from v0.14.0.
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
Use devicetree instead of Kconfig to configure the board control
switches in nRF9160 DK:
- add binding for the switches that provide optional signal routings
on this board
- add binding for the GPIO interface that can be used for communication
(e.g. UART based) between the nRF9160 and the nRF52840 on the DK,
and add GPIO mapping for this interface so that its lines can be used
without caring about of actual pin numbers on both sides
- add binding for one GPIO line chosen from the above interface that is
to allow the nRF9160 to reset the nRF52840
- update accordingly dts files and board specific code for both board
definitions associated with the DK
- introduce .dtsi files that can be included from dts overlays in order
to facilitate the use of the above GPIO interface; modify the overlay
in the hci_uart sample to provide an example of use of those files
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
There is a hardcoded macro in Winc1500 HAL SPI driver
that would prevent the driver from working.
This macro is now defined only based on KConfig entry.
This KConfig entry is by default not set.
To enable, set "CONFIG_WINC1500_DRV_USE_OLD_SW=y"
in proj.conf or board.conf
Signed-off-by: Raja D. Singh <rdsingh@iotwizards.com>
This adds a new qemu_x86_virt board where code and data are
mapped in virtual address space and is actually executing within
virtual address space.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
When the kernel links in virtual address space, the data
structures needed for the z_phys_map() no longer point to physical
addresses (which are required for z_phys_map() to work). So skips
these tests if CONFIG_KERNEL_LINK_IN_VIRT=y.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
For some unknown reason, the pagetable address for _df_tss.cr3
did not get translated from virtual to physical. However,
the translation is done if the pointer to pagetable is obtained
through reference to the first array element (instead of simply
through the name of array). Without CR3 pointing to the page
table via physical address, double fault does not work. So
fixing this by being explicit with the page table pointer.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
When adding a new thread to memory domain, there is a NULL check
to figure out if a thread is being migrated to another memory
domain. However, the NULL check is AFTER physical-to-virtual
address translation which means (NULL + offset) != NULL anymore.
This results in calling reset_region() with an invalid page table
pointer. Fix this by doing the NULL check before address
translation.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
When linking in virtual address space, we still need physical
addresses in SRAM to be mapped so platform can boot from physical
memory and to access structure necessary for boot (e.g. GDT and
IDT). So we need to enlarge the reserved space for page table
to accommodate this.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
We have been having the assumption that the physical memory
is identity-mapped to virtual address space. However, with
the ability to set CONFIG_KERNEL_VM_BASE separately from
CONFIG_SRAM_BASE_ADDRESS, the assumption is no longer valid.
This changes the boot code in x86 32-bit, so that once
the page table is loaded, we can proceed with executing in
the virtual address space. So do a long jump to virtual
address just before calling z_x86_prep_c. From this point on,
code execution is in virtual address space.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
When linking in virtual address space, we still need physical
addressed in SRAM to be mapped so platform can boot from physical
memory and to access structure necessary for boot (e.g. GDT and
IDT). So identity maps the kernel in SRAM.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
When the kernel is mapped into virtual address space
that is different than the physical address space,
the dynamic GDT generation uses the virtual addresses.
However, the GDT table is required at boot before
page table is loaded where the virtual addresses are
invalid. So make sure GDT generation is using
physical addresses.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
There is an assumption made in the page table generation code
that the kernel would occupy the same physical and virtual
addresses. However, we may want to map the kernel into
a virtual address space which differs from kernel's physical
address space. For example, with demand paging enabled on
kernel code and data, we can accommodate kernel that is
larger than physical memory size, and may want to utilize
a bigger virtual address space. So add address translation
in the gen_mmu.py script for this.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
This adds virtual address translation to a few variables
used in crt0.S. This is needed as they are linked at
virtual addresses but before page table is loaded,
they are not available at virtual addresses and must be
referred via physical addresses.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
When feeding &z_shared_kernel_page_start directly to
Z_X86_PHYS_ADDR(), the compiler would complain array subscript
out of bound if linking in virtual address space. So cast it
into uintptr_t first before translation.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
checkpatch misinterprets the macro that generates event data
structures as being code rather than more data. This code has not
been changed, but rearrangement of code around it causes a false
positive when the aggregate changes are checked for style.
Add an extra line to eliminate the warning.
Signed-off-by: Peter Bigot <peter.bigot@nordicsemi.no>
Now that the old API has been reimplemented with the new API remove
the old implementation and its tests.
Signed-off-by: Peter Bigot <peter.bigot@nordicsemi.no>
The new API cannot be used from userspace because it is not merely a
wrapper around existing userspace-capable objects (threads and
queues), but instead requires much more complex and lower-level access
to memory that can't be touched from userspace. The vast majority of
work queue users are operating from privileged mode, so there's little
motivation to go through the pain and complexity of converting all
functions to system calls.
Copy the necessary pieces of the existing userspace work queue API out
and expose them with new names and types:
* k_work_handler_t becomes k_work_user_handler_t
* k_work becomes k_work_user
* k_work_q becomes k_work_user_q
etc. Because the replacement API cannot use the same types new API
names are also introduced to make it more clear that the userspace
work queue API is a separate functionality.
Signed-off-by: Peter Bigot <peter.bigot@nordicsemi.no>
Replace legacy API with new API. Note that this driver uses the
schedule, not reschedule, API, since triggers for delay never overlap.
Signed-off-by: Peter Bigot <peter.bigot@nordicsemi.no>
