Both operands of an operator in which the usual arithmetic
conversions are performed shall have the same essential
type category.
Signed-off-by: Flavio Ceolin <flavio.ceolin@intel.com>
Both operands of an operator in which the usual arithmetic
conversions are performed shall have the same essential
type category.
Signed-off-by: Flavio Ceolin <flavio.ceolin@intel.com>
Both operands of an operator in which the usual arithmetic
conversions are performed shall have the same essential
type category.
Signed-off-by: Flavio Ceolin <flavio.ceolin@intel.com>
Both operands of an operator in which the usual arithmetic
conversions are performed shall have the same essential
type category.
Signed-off-by: Flavio Ceolin <flavio.ceolin@intel.com>
Both operands of an operator in which the usual arithmetic
conversions are performed shall have the same essential
type category.
Signed-off-by: Flavio Ceolin <flavio.ceolin@intel.com>
Projects based on native_posix get a warning indicating that the
LOG_MODE_IMMEDIATE choice symbol is selected but no symbol ended up as
the choice selection.
Only set the logging mode if logging is enabled.
Signed-off-by: Keith Short <keithshort@google.com>
In CI we typically build for "default" platforms. However some
testcases that set "platform_allow" may have no overlap with the default
platforms and thus thoses testcases will not get built.
Change the platform selection logic in these cases to set the platforms
to the list of allowed platforms ("platform_allow") in the testcase.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
With this patch, the UCPD1 _CC1 and _CC2 pins
are disabling the USB Type-C and Power Delivery Dead Battery.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
With this patch, the UCPD1 _CC1 and _CC2 pins
are disabling the USB Type-C and Power Delivery Dead Battery.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
With this patch, the UCPD1 _CC1 and _CC2 pins
are disabling the USB Type-C and Power Delivery Dead Battery.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
ESP32 requires some content as fatal.c rodata to be
placed into RAM to allow cache disabled exceptions.
The consequence is that it will trigger missing log_strdup
call when normal exception is called. Disabling that by default
fix the error and stops terminal output flooding warning event.
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
The source clock of the watchdog module is selected to the input of T0
timer, not output. Correct the drawing in case confusing the users.
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
This CL adds support for console expired mechanism. It implements the
notification to power management module that the module for console is
in use. If the interval that module doesn't receive any input message
exceeds CONFIG_SOC_POWER_CONSOLE_EXPIRED_TIMEOUT, the power management
module is allowed to enter deep sleep mode. This mechanism gives a
window in which the users can organize console input.
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
This CL introduces two configuration options which allows a notification
to the power management module that the UART console module is in use
now. If the interval of console module doesn't receive any input message
exceeds expired timeout, the power management module is allowed to enter
sleep/deep sleep state and turn off the clock of console module.
This mechanism gives a window in which the users can organize input
message if CONFIG_PM is enabled.
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
NPCX watchdog driver has a WDT_NPCX_DELAY_CYCLES for delay the watchdog
reset time after the watchdog timeout. For some systems, users would
like to use the watchdog timeout ISR but don't reset the chip
immediately. Let the system have the final chance to ongoing the system
before the real hardware reset time. Removing the watchdog reset
waiting loop in ISR lets users decide whether wait for watchdog reset
by themself.
Signed-off-by: Wealian Liao <WHLIAO@nuvoton.com>
The GSG link is no longer valid. This commit fixes the link to
use the site recommended by ACRN developers.
Fixes#34149
Signed-off-by: Jennifer Williams <jennifer.m.williams@intel.com>
Add a note in the Kconfig help text that explains why Hard ABI
is not possible on builds with TF-M.
Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
When building with TFM, the app is linked with libraries built by the
TFM build system. TFM is always built with -msoft-float which is
equivalent to -mfloat-abi=soft. FP_HARDABI adds -mfloat-abi=hard
which gives errors when linking with the libs from TFM since they are
built with a different ABI.
Fixes https://github.com/zephyrproject-rtos/zephyr/issues/33956
Signed-off-by: Øyvind Rønningstad <oyvind.ronningstad@nordicsemi.no>
Move the LLL done event handling from ULL to LLL, this
reduces CPU utilization and reduces overhead between radio
events.
Fixes#21993.
Signed-off-by: Vinayak Kariappa Chettimada <vich@nordicsemi.no>
Defer the event early abort so that lll_done does not get
recursively invoked when called inside prepare callback.
Signed-off-by: Vinayak Kariappa Chettimada <vich@nordicsemi.no>
There is a race between the pipeline enqueue by the ULL
context when processing the LLL done event, and the
pipeline queue by the ticker timeout for a new radio
event. This caused an already enqueued event prepare to be
placed after the newly arrived request to enqueue a prepare
by ticker timeout.
Fix this race by placing the new prepare in the pipeline
instead of starting the event, when ULL is still processing
the LLL done event.
As ticker timeout and ULL processing of LLL done event are
in the same ULL_HIGH context, the pipeline handling is safe
with the order of prepares maintained correctly.
Signed-off-by: Vinayak Kariappa Chettimada <vich@nordicsemi.no>
We can't do atomic memory operations before the MMU is on. Let's create
a code path to set up MMU page tables without any lock. There is
obviously no concurrency issues at this stage.
Signed-off-by: Nicolas Pitre <npitre@baylibre.com>
Add include <bluetooth/mesh/msg.h> into <bluetooth/mesh/access.h> to get
definition of 'struct bt_mesh_msg_ctx'.
We see this when trying to build the mesh_badge sample for the
reel_board.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
The commit fixes problem with nrfjprog runner for west flash,
that has been introduced with latest changes to BuildConfiguration
class.
Signed-off-by: Dominik Ermel <dominik.ermel@nordicsemi.no>
GIC_INTID_SPURIOUS is a GIC-specific intid so it's not valid for custom
interrupt controllers. Rework a bit the logic by comparing the intid to
the maximum intid possible instead.
Signed-off-by: Carlo Caione <ccaione@baylibre.com>
On STM32L5 based boards, rework the TFM build/flash instructions
to minimize potential confusions.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Currently _curr_cpu is only used by the get_cpu macro to quickly access
the cpu struct. This is not really necessary because we can access to
the struct by directly referencing &(_kernel.cpus[cpu_num]) in assembly
Signed-off-by: Carlo Caione <ccaione@baylibre.com>
Commit d6c34c4644 changed the behavior
slightly but didn't update the documentation. The callback will now be
reset to NULL once the key is generated. Calling bt_pub_key_gen()
multiple times before the key is finished would result in creation of an
infinite loop. This could happen when an application calls mesh_init()
and mesh_reset() in quick succession. Clarify the behavior of the API in
the documentation.
Also passing a NULL argument would result in an undefined behavior, so
add a check to match the behavior described in documentation.
Signed-off-by: Michał Narajowski <michal.narajowski@codecoup.pl>
NXP ls1046a is SoC includes the following functions and features:
1. Four 32/64-bit Arm v8 A72 CPUs
2. Cache coherent interconnect (CCI-400)
3. One 32/64-bit DDR4 SDRAM memory controller with ECC
4. Peripheral interfaces include DPAA network, PCIe, USB, SPI,
GPIO, UART, SDHC, IFC, LPUART ...
Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.com>
The stm32 wwdg driver was currently tested only on disco_l475_iot1.
Additionally add nucleo_f091rc, such that one board with an CM0 core is
tested. And add nucleo_g431rb, that one board is included that has
newer register mapping and a 128 prescaler.
Signed-off-by: Thomas Stranger <thomas.stranger@outlook.com>
As older series supported only 4 different prescaler values the
highest prescaler value was hardcoded. Newer series support 8
programmable prescaler values, therefore take the allowed values from
ll_wwdg header file.
Signed-off-by: Thomas Stranger <thomas.stranger@outlook.com>
Series STM32G0, STM32G4, STM32H7, STM32L5, STM32WB, STM32WL have
a newer wwdg ip and store the prescaler value not in bits[8:7],
but bits bits[13:11], use the definitions from ll to account for that.
Remove IS_WWDG_PRESCALER, this is not required as the prescaler
is not calculated, but known valid prescaler values are tested until a
valid counter is found.
Signed-off-by: Thomas Stranger <thomas.stranger@outlook.com>
Cortex M0 Series only have two interrupt priority bits,
nevertheless all series set the priority per default to the invalid
value of 7.
Signed-off-by: Thomas Stranger <thomas.stranger@outlook.com>
Add tests that validate the behaviour of providing NULL as a data
pointer to discard whatever data is in the ring buffer.
Signed-off-by: Jordan Yates <jordan.yates@data61.csiro.au>
Allow NULL data buffers to be provided to `ring_buf_get` and
`ring_buf_item_get`, in which case data will be discarded instead of
copied out to the user.
Fixes#33488.
Signed-off-by: Jordan Yates <jordan.yates@data61.csiro.au>
Add Alexandre and François as collaborators on STM32 Platforms.
Additionally, add one naming for stm32 boards.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Update the binding for how we represent pin data to support child
nodes with a nxp,kinetis-pins property that has the pin data.
For example:
UART0_CTS_PTA0: uart0_cts_pta0 {
nxp,kinetis-port-pins = < 0 2 >;
};
Also pull in pincfg-node.yaml to get various common pin flags like
"bias-pull-up", "drive-open-drain", etc.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
