Provide CONFIG macros for clocks bits and bus properties in fixup
files and use them to simplify logic in uart devices instanciation
code
Fixes#10448
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
The ARMv8-M Memory Protection Unit document indicates that a DMB
instruction must be used before disabling the MPU in order to force
outstanding memory transactions.
The ARMv7-M documentation is less clear about that, and only specifies
that a DSB instruction followed by a ISB instruction must be used
before enabling the MPU, which is already the case. The ARMv7-M and
ARMv8-M MPU are relatively similar to believe the same sequence should
be used for disabling it.
This patch therefore adds a DMB instruction before disabling the MPU.
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
In Zephyr on Cortex-M SoCs with both the ARM MPU and the cache enabled,
there are 3 possible states and associated configuration for the RAM
cache attributes:
- MPU disabled WBWA non-shareable
- MPU enabled, background RAM region WBWA non-shareable
- MPU enabled, thread RAM region WBWA shareable
In practice this means than the thread RAM region toggles from
shareable to non-shareable on each context change.
However the Cortex-M7 SoC does not support the WBWA shareable
configuration and fallback to simpler caching configuration. The
Technical Reference Manual states:
"By default, only Normal, Non-shareable memory regions can be cached
in the RAMs. Caching only takes place if the appropriate cache is
enabled and the memory type is cacheable. Shared cacheable memory
regions can be cached if CACR.SIWT is set to 1."
Similar indications can be found in the documentation from various
vendors: ST (AN4838), NXP (AN12042) and Atmel (AN15679).
It means that the thread RAM regions are either not cached (CACR.SIWT=0,
default) or WBWT cached (CACR.SIWT=1). This causes a performance issue.
In addition before switching a region from cached to non-cached and
vice-versa, the existing MPU code does not perform cache clean and/or
invalidate operations. This might cause data loss or corruption.
We should therefore change the RAM cache attributes to make them always
consistent. This patches change the thread/application RAM region from
WBWA shareable to WBWA non-shareable. This is done for all ARMv7-M SoCs
with an ARM MPU, however other SoCs (M0+, M3, M4) do not have cache, so
their behaviour should be unchanged.
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
Move misc/Kconfig options to where they belong. misc/Kconfig was used as
a catch-all, but we are now able to put things in a better place.
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Add a new 'Kconfig tips and best practices' page that covers some
Kconfig best practices, tips, and arcana, like the following:
- What should be turned into a Kconfig symbol?
- Best practices and pitfalls for 'select'
- Factoring out common dependencies
- Kconfig shorthands
- Redundant defaults
- Explanations of various more obscure Kconfig features, like 'imply',
optional prompts, optional choices, and 'visible if'
Link the new page in the sidebar (under Developer Guides), the
application development primer, and the architecture and board porting
guides.
Perhaps other, more Zephyr-specific information could be added later on
as well, but this is a good start.
Include some other Kconfig-related documentation improvements as well:
- In the application development primer, give 'CONFIG_FOO=n' as the way
to set a bool symbol to 'n', instead of '# CONFIG_FOO is not set'.
That seems to be what people usually do in practice in Zephyr.
Explain why '# CONFIG_FOO is not set' works as well. There's a
technical reason for it, related to Make.
- Mention that the recommended syntax for referencing environment
variables is now $(FOO) (which uses the Kconfig preprocessor)
- Mention that the kconfiglib.py docstring has more in-depth
information about how symbol values are calculated.
Signed-off-by: Ulf Magnusson <Ulf.Magnusson@nordicsemi.no>
CONFIG_ADC_QMSI and CONFIG_ADC_QMSI_SS aren't defined anywhere so
remove the dead CMake references to them.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
CONFIG_ADC_DW_REPETITIVE and CONFIG_ADC_DW_DUMMY_CONVERSION aren't
defined anywhere so remove the associated code for these Kconfig
symbols.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
move CI scripting to a dedicated script. For example, to simulate what
is run in CI when a pull request is submitted:
./scripts/ci/run_ci.sh -b master -r upstream -p
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Case when bus parent has more than one compatible was not treated
correctly. Use get_compat() method which returns first compat
in case several compats are available
Fixes#11121
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
The channels assigned to the controller are reordered so that the ones
previously used and now available for other purposes have continuous
numbers. When the controller can take advantage of the pre-programmed
PPI channels (when TIMER0 is used as the event timer), the now free
channels are 0-4, when it cannot, it is the channel 0.
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
Several PPI channels in nRF5 family SoCs are pre-programmed with fixed
settings. A few of them can be used in the bluetooth controller instead
of the freely programmable ones that are used currently. This commit
makes such replacements where possible so that the universal channels
can be left available for other purposes.
This commit also removes macros used previously in calls to functions
enabling and disabling particular PPI channels (as it is sufficient
to use the BIT macro to set bits corresponding to the channel numbers)
to prevent such problems like the one introduces by commit
9d1ca9c390 (channel 18 changed to 17
but the related macro definition not updated).
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
Nios2 is trying to use global pointer register to access variables
smaller than 8 bytes. GPR range is limited to 64 bytes and apparently
does not handle well variables placed in custom sections.
Current workaround is to increase logger structures (const and dynamic)
size (+8 bytes for dynamic, +4 bytes for constant). Then GPR is not
used and application can be linked. The downside is increase of memory
usage:
- ROM: <num_of_log_modules>*4 bytes
- RAM: <num_of_log_modules>*8 bytes (if runtime filtering is enabled)
Signed-off-by: Krzysztof Chruscinski <krzysztof.chruscinski@nordicsemi.no>
Changed LOG_MODULE_REGISTER and LOG_MODULE_DECLARE macros to take log
level as optional parameter. LOG_MODULE_DECLARE can now also be used
in static inline functions in headers. Added LOG_LEVEL_SET macro
which is used when instance logging API is used to indicate maximal
log level compiled into the file.
Signed-off-by: Krzysztof Chruscinski <krzysztof.chruscinski@nordicsemi.no>
Couple of findings which were revealed after changing
LOG_MODULE_REGISTER macro:
- missing semicolons after LOG_MODULE_REGISTER()
- missing LOG_LEVEL defines
- other
Signed-off-by: Krzysztof Chruscinski <krzysztof.chruscinski@nordicsemi.no>
Log configuration was included only in case NET_L2_IEEE802154 was
enabled. In case of open thread this is not the case.
Signed-off-by: Krzysztof Chruscinski <krzysztof.chruscinski@nordicsemi.no>
Add #pwm-cells to the i.MX PWM binding and dts files. This is to
support have a pwms clients work properly.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Add #pwm-cells to the STM32 PWM binding and dts files. This is to
support have a pwms clients work properly.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
.gnu.linkonce is an internal undocumented ld feature.
Just use __weak, which does the same thing we want.
This is only done for _sw_isr_table. _irq_vector_table
is left alone due to unwanted interactions between
__weak and the ld KEEP() directive.
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
We now place the linker directives for the SW ISR table
in the common linker scripts, instead of repeating it
everywhere.
The table will be placed in RAM if dynamic interrupts are
enabled.
A dedicated section is used, as this data must not move
in between build phases.
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
If dynamic interrupts are enabled, a set of trampoline stubs
are generated which transfer control to a common dynamic
interrupt handler function, which then looks up the proper
handler and parameter and then executes the interrupt.
Based on the prior x86 dynamic interrupt implementation which
was removed from the kernel some time ago, and adapted to
changes in the common interrupt handling code, build system,
and IDT generation tools.
An alternative approach could be to read the currently executing
vector out of the APIC, but this is a much slower operation.
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
Update interrupts.rst with information on how to use dynamic
interrupts. As they are used in the same way as IRQ_CONNECT(),
not much needs to be written.
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
In the past the capability to install interrupts at runtime was
removed due to lack of use-cases for Zephyr's intended targets.
Now we want to support hypervisor applications like ACRN where
virtual devices are presented to the kernel using PCI enumeration,
and the interrupt configuration is not known at build time.
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
The recently released version 0.13.0 of pyocd does not install cleanly
in linux and prevents installation of requirements.txt. Locking pyocd to
version 0.12.0 is a temporary workaround until problem is solved by
pyocd maintainers.
Signed-off-by: Mikkel Jakobsen <mikkel.aunsbjerg@prevas.dk>
The overlay-e1000.conf can be used for example with Qemu
which has support for e1000 ethernet driver.
Signed-off-by: Jukka Rissanen <jukka.rissanen@linux.intel.com>
Introduce new Kconfig option for selecting either slip or ethernet
connectivity to host.
Signed-off-by: Jukka Rissanen <jukka.rissanen@linux.intel.com>
Newer DTC now warns about mismatch between the reg and unit-address.
Most of these cases are due to case not matching, so fix thoses so
everything is lowercase.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
In #10543 some include directives are modified to include some
folders in the path to the nrfx hal headers.
This would break things with the previous nRF52 HW models as the
replacement hal files were not placed in a folder matching that
path, and the include path was not pointing directly at the folder
containing the files.
Therefore, require the latest HW models version (which replicates
that folder structure), and add a new -I for the compiler 2 folders
higher.
Signed-off-by: Alberto Escolar Piedras <alpi@oticon.com>
Change the label GPIO_KEYS_BUTTON_0_GPIO_CONTROLLER that is generated
for the DT node directly to the corresponding one generated through
the "sw0" alias (i.e. SW0_GPIO_CONTROLLER) to make it consistent with
other DT related labels used in this code (SW0_* and LED?_*).
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
Intel S1000 has 4MB of internal memory.
In DTS it was defined as 3MB and is now updated to 4MB.
Signed-off-by: Sathish Kuttan <sathish.k.kuttan@intel.com>
Provide necessary error handling for `lis2dh_reg_read_byte` function
which might fail.
Also, use a common `status` variable to be used for storing the
error code.
Fixes#10590
Coverity-CID: 188733
Signed-off-by: Himanshu Jha <himanshujha199640@gmail.com>
The Kconfig variable for selecting neural network accelerator driver(s)
was changed from NEURAL_NET to NEURAL_NET_ACCEL
The CMakeLists.txt however, was not updated to use the updated variable
This commit updates CMakeLists.txt to include neural_net if
CONFIG_NEURAL_NET_ACCEL is defined.
Signed-off-by: Sathish Kuttan <sathish.k.kuttan@intel.com>
The code referenced CONFIG_SHELL_VT100_COLORS_ENABLED which does not
exist. Its mostly likely that CONFIG_SHELL_VT100_COLORS was meant
to be tested instead.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Now that we set LED info in the device tree for all boards we don't need
to special case handle in the name/led pin (it comes from DT). We can
also remove include board.h.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
This commit contributes a patch to the Arm Cortex-M linker
script, which guarantees that the linker sections for shared
memory and the application memory will have sufficient padding
in between, so that the latter will start from an address that
is 32-byte aligned. This is required for ensuring that the MPU
regions defined using the start and end addresses of the two
sections will not overlap. The patch targets ARMv8-M MPU with
no requirement for power-of-two alignment and size.
Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
The endif comment block is for CONFIG_BT_FIXED_PASSKEY not
CONFIG_SMP_FIXED_PASSKEY. Fix the comment to match.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
