bluetooth: controller: nrf5: Use pre-programmed PPI channels
Several PPI channels in nRF5 family SoCs are pre-programmed with fixed
settings. A few of them can be used in the bluetooth controller instead
of the freely programmable ones that are used currently. This commit
makes such replacements where possible so that the universal channels
can be left available for other purposes.
This commit also removes macros used previously in calls to functions
enabling and disabling particular PPI channels (as it is sufficient
to use the BIT macro to set bits corresponding to the channel numbers)
to prevent such problems like the one introduces by commit
9d1ca9c390 (channel 18 changed to 17
but the related macro definition not updated).
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
This commit is contained in:
Andrzej Głąbek
Anas Nashif
parent
f75d11adb2
commit
589b65e72d
7 changed files with 301 additions and 249 deletions
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@ -434,7 +434,10 @@ config BT_CTLR_SW_SWITCH_SINGLE_TIMER
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(+) removes jitter for HCTO implementation
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(-) introduces drifting to the absolute time inside BLE
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events, that increases linearly with the number of
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packets exchanged in the event.
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packets exchanged in the event
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(-) makes it impossible to use most of the pre-programmed
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PPI channels for the controller, resulting in 4 channels
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less left for other uses
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if BT_CONN
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@ -15,11 +15,11 @@
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#include "ll_sw/pdu.h"
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#include "radio_nrf5.h"
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#include "nrf_radio.h"
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#include "nrf_rtc.h"
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#include "nrf_ccm.h"
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#include "nrf_timer.h"
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#include "nrf_ppi.h"
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#include <nrfx/hal/nrf_radio.h>
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#include <nrfx/hal/nrf_rtc.h>
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#include <nrfx/hal/nrf_ccm.h>
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#include <nrfx/hal/nrf_timer.h>
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#include <nrfx/hal/nrf_ppi.h>
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#if defined(CONFIG_SOC_SERIES_NRF51X)
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#define RADIO_PDU_LEN_MAX (BIT(5) - 1)
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@ -257,8 +257,8 @@ void radio_tx_enable(void)
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void radio_disable(void)
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{
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#if !defined(CONFIG_BT_CTLR_TIFS_HW)
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nrf_ppi_channels_disable(HAL_SW_SWITCH_TIMER_CLEAR_PPI_DISABLE |
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HAL_SW_SWITCH_GROUP_TASK_ENABLE_PPI_DISABLE);
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nrf_ppi_channels_disable(BIT(HAL_SW_SWITCH_TIMER_CLEAR_PPI) |
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BIT(HAL_SW_SWITCH_GROUP_TASK_ENABLE_PPI));
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nrf_ppi_group_disable(SW_SWITCH_TIMER_TASK_GROUP(0));
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nrf_ppi_group_disable(SW_SWITCH_TIMER_TASK_GROUP(1));
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#endif /* !CONFIG_BT_CTLR_TIFS_HW */
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@ -439,7 +439,7 @@ static void sw_switch(u8_t dir, u8_t phy_curr, u8_t flags_curr, u8_t phy_next,
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sw_tifs_toggle);
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nrf_ppi_channels_enable(
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HAL_SW_SWITCH_TIMER_S8_DISABLE_PPI_ENABLE);
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BIT(HAL_SW_SWITCH_TIMER_S8_DISABLE_PPI));
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} else {
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/* Switching to TX after RX on LE 1M/2M PHY */
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u8_t ppi_dis =
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@ -505,8 +505,8 @@ static void sw_switch(u8_t dir, u8_t phy_curr, u8_t flags_curr, u8_t phy_next,
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nrf_timer_cc_write(SW_SWITCH_TIMER, cc, 1);
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}
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nrf_ppi_channels_enable(HAL_SW_SWITCH_TIMER_CLEAR_PPI_ENABLE |
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HAL_SW_SWITCH_GROUP_TASK_ENABLE_PPI_ENABLE);
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nrf_ppi_channels_enable(BIT(HAL_SW_SWITCH_TIMER_CLEAR_PPI) |
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BIT(HAL_SW_SWITCH_GROUP_TASK_ENABLE_PPI));
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#if defined(CONFIG_BT_CTLR_SW_SWITCH_SINGLE_TIMER)
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/* Since the event timer is cleared on END, we
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@ -553,8 +553,8 @@ void radio_switch_complete_and_disable(void)
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(RADIO_SHORTS_READY_START_Msk | RADIO_SHORTS_END_DISABLE_Msk);
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#if !defined(CONFIG_BT_CTLR_TIFS_HW)
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nrf_ppi_channels_disable(HAL_SW_SWITCH_TIMER_CLEAR_PPI_DISABLE |
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HAL_SW_SWITCH_GROUP_TASK_ENABLE_PPI_DISABLE);
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nrf_ppi_channels_disable(BIT(HAL_SW_SWITCH_TIMER_CLEAR_PPI) |
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BIT(HAL_SW_SWITCH_GROUP_TASK_ENABLE_PPI));
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#endif /* !CONFIG_BT_CTLR_TIFS_HW */
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}
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@ -638,21 +638,22 @@ void radio_tmr_status_reset(void)
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nrf_rtc_event_disable(NRF_RTC0, RTC_EVTENCLR_COMPARE2_Msk);
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nrf_ppi_channels_disable(
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HAL_RADIO_ENABLE_ON_TICK_PPI_DISABLE |
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HAL_EVENT_TIMER_START_PPI_DISABLE |
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HAL_RADIO_READY_TIME_CAPTURE_PPI_DISABLE |
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HAL_RADIO_RECV_TIMEOUT_CANCEL_PPI_DISABLE |
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HAL_RADIO_DISABLE_ON_HCTO_PPI_DISABLE |
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HAL_RADIO_END_TIME_CAPTURE_PPI_DISABLE |
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BIT(HAL_RADIO_ENABLE_TX_ON_TICK_PPI) |
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BIT(HAL_RADIO_ENABLE_RX_ON_TICK_PPI) |
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BIT(HAL_EVENT_TIMER_START_PPI) |
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BIT(HAL_RADIO_READY_TIME_CAPTURE_PPI) |
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BIT(HAL_RADIO_RECV_TIMEOUT_CANCEL_PPI) |
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BIT(HAL_RADIO_DISABLE_ON_HCTO_PPI) |
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BIT(HAL_RADIO_END_TIME_CAPTURE_PPI) |
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#if defined(CONFIG_BT_CTLR_PHY_CODED)
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#if defined(CONFIG_SOC_NRF52840)
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HAL_TRIGGER_RATEOVERRIDE_PPI_DISABLE |
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BIT(HAL_TRIGGER_RATEOVERRIDE_PPI) |
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#if !defined(CONFIG_BT_CTLR_TIFS_HW)
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HAL_SW_SWITCH_TIMER_S8_DISABLE_PPI_DISABLE |
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BIT(HAL_SW_SWITCH_TIMER_S8_DISABLE_PPI) |
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#endif /* !CONFIG_BT_CTLR_TIFS_HW */
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#endif /* CONFIG_SOC_NRF52840 */
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#endif /* CONFIG_BT_CTLR_PHY_CODED */
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HAL_TRIGGER_CRYPT_PPI_DISABLE);
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BIT(HAL_TRIGGER_CRYPT_PPI));
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}
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void radio_tmr_tifs_set(u32_t tifs)
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@ -683,10 +684,8 @@ u32_t radio_tmr_start(u8_t trx, u32_t ticks_start, u32_t remainder)
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nrf_rtc_cc_set(NRF_RTC0, 2, ticks_start);
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nrf_rtc_event_enable(NRF_RTC0, RTC_EVTENSET_COMPARE2_Msk);
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nrf_ppi_channel_endpoint_setup(HAL_EVENT_TIMER_START_PPI,
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HAL_EVENT_TIMER_START_EVT,
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HAL_EVENT_TIMER_START_TASK);
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nrf_ppi_channels_enable(HAL_EVENT_TIMER_START_PPI_ENABLE);
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hal_event_timer_start_ppi_config();
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nrf_ppi_channels_enable(BIT(HAL_EVENT_TIMER_START_PPI));
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hal_radio_enable_on_tick_ppi_config_and_enable(trx);
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@ -702,9 +701,7 @@ u32_t radio_tmr_start(u8_t trx, u32_t ticks_start, u32_t remainder)
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nrf_timer_task_trigger(SW_SWITCH_TIMER, NRF_TIMER_TASK_START);
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#endif /* !CONFIG_BT_CTLR_SW_SWITCH_SINGLE_TIMER */
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nrf_ppi_channel_endpoint_setup(HAL_SW_SWITCH_TIMER_CLEAR_PPI,
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HAL_SW_SWITCH_TIMER_CLEAR_PPI_EVT,
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HAL_SW_SWITCH_TIMER_CLEAR_PPI_TASK);
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hal_sw_switch_timer_clear_ppi_config();
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#if !defined(CONFIG_BT_CTLR_PHY_CODED) || !defined(CONFIG_SOC_NRF52840)
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/* NOTE: PPI channel group disable is setup explicitly in sw_switch
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@ -786,31 +783,18 @@ void radio_tmr_hcto_configure(u32_t hcto)
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{
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nrf_timer_cc_write(EVENT_TIMER, 1, hcto);
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nrf_ppi_channel_endpoint_setup(HAL_RADIO_RECV_TIMEOUT_CANCEL_PPI,
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HAL_RADIO_RECV_TIMEOUT_CANCEL_PPI_EVT,
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HAL_RADIO_RECV_TIMEOUT_CANCEL_PPI_TASK);
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nrf_ppi_channel_endpoint_setup(HAL_RADIO_DISABLE_ON_HCTO_PPI,
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HAL_RADIO_DISABLE_ON_HCTO_PPI_EVT,
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HAL_RADIO_DISABLE_ON_HCTO_PPI_TASK);
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nrf_ppi_channels_enable(HAL_RADIO_RECV_TIMEOUT_CANCEL_PPI_ENABLE |
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HAL_RADIO_DISABLE_ON_HCTO_PPI_ENABLE);
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hal_radio_recv_timeout_cancel_ppi_config();
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hal_radio_disable_on_hcto_ppi_config();
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nrf_ppi_channels_enable(BIT(HAL_RADIO_RECV_TIMEOUT_CANCEL_PPI) |
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BIT(HAL_RADIO_DISABLE_ON_HCTO_PPI));
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}
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void radio_tmr_aa_capture(void)
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{
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nrf_ppi_channel_endpoint_setup(HAL_RADIO_READY_TIME_CAPTURE_PPI,
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HAL_RADIO_READY_TIME_CAPTURE_PPI_EVT,
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HAL_RADIO_READY_TIME_CAPTURE_PPI_TASK);
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nrf_ppi_channel_endpoint_setup(HAL_RADIO_RECV_TIMEOUT_CANCEL_PPI,
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HAL_RADIO_RECV_TIMEOUT_CANCEL_PPI_EVT,
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HAL_RADIO_RECV_TIMEOUT_CANCEL_PPI_TASK);
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nrf_ppi_channels_enable(
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HAL_RADIO_READY_TIME_CAPTURE_PPI_ENABLE |
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HAL_RADIO_RECV_TIMEOUT_CANCEL_PPI_ENABLE);
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hal_radio_ready_time_capture_ppi_config();
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hal_radio_recv_timeout_cancel_ppi_config();
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nrf_ppi_channels_enable(BIT(HAL_RADIO_READY_TIME_CAPTURE_PPI) |
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BIT(HAL_RADIO_RECV_TIMEOUT_CANCEL_PPI));
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}
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u32_t radio_tmr_aa_get(void)
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@ -838,11 +822,8 @@ u32_t radio_tmr_ready_get(void)
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void radio_tmr_end_capture(void)
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{
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nrf_ppi_channel_endpoint_setup(HAL_RADIO_END_TIME_CAPTURE_PPI,
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HAL_RADIO_END_TIME_CAPTURE_PPI_EVT,
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HAL_RADIO_END_TIME_CAPTURE_PPI_TASK);
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nrf_ppi_channels_enable(HAL_RADIO_END_TIME_CAPTURE_PPI_ENABLE);
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hal_radio_end_time_capture_ppi_config();
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nrf_ppi_channels_enable(BIT(HAL_RADIO_END_TIME_CAPTURE_PPI));
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}
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u32_t radio_tmr_end_get(void)
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@ -952,20 +933,16 @@ void radio_gpio_pa_lna_enable(u32_t trx_us)
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{
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nrf_timer_cc_write(EVENT_TIMER, 2, trx_us);
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HAL_ENABLE_PALNA_PPI_REGISTER_EVT = HAL_ENABLE_PALNA_PPI_EVT;
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HAL_ENABLE_PALNA_PPI_REGISTER_TASK = HAL_ENABLE_PALNA_PPI_TASK;
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HAL_DISABLE_PALNA_PPI_REGISTER_EVT = HAL_DISABLE_PALNA_PPI_EVT;
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HAL_DISABLE_PALNA_PPI_REGISTER_TASK = HAL_DISABLE_PALNA_PPI_TASK;
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nrf_ppi_channels_enable(HAL_ENABLE_PALNA_PPI_ENABLE
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| HAL_DISABLE_PALNA_PPI_ENABLE);
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hal_enable_palna_ppi_config();
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hal_disable_palna_ppi_config();
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nrf_ppi_channels_enable(BIT(HAL_ENABLE_PALNA_PPI) |
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BIT(HAL_DISABLE_PALNA_PPI));
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}
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void radio_gpio_pa_lna_disable(void)
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{
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nrf_ppi_channels_disable(HAL_ENABLE_PALNA_PPI_DISABLE |
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HAL_DISABLE_PALNA_PPI_DISABLE);
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nrf_ppi_channels_disable(BIT(HAL_ENABLE_PALNA_PPI) |
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BIT(HAL_DISABLE_PALNA_PPI));
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}
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#endif /* CONFIG_BT_CTLR_GPIO_PA_PIN || CONFIG_BT_CTLR_GPIO_LNA_PIN */
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@ -1013,11 +990,8 @@ void *radio_ccm_rx_pkt_set(struct ccm *ccm, u8_t phy, void *pkt)
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CCM_RATEOVERRIDE_RATEOVERRIDE_Pos) &
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CCM_RATEOVERRIDE_RATEOVERRIDE_Msk;
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HAL_TRIGGER_RATEOVERRIDE_PPI_REGISTER_EVT =
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HAL_TRIGGER_RATEOVERRIDE_PPI_EVT;
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HAL_TRIGGER_RATEOVERRIDE_PPI_REGISTER_TASK =
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HAL_TRIGGER_RATEOVERRIDE_PPI_TASK;
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nrf_ppi_channels_enable(HAL_TRIGGER_RATEOVERRIDE_PPI_ENABLE);
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hal_trigger_rateoverride_ppi_config();
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nrf_ppi_channels_enable(BIT(HAL_TRIGGER_RATEOVERRIDE_PPI));
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break;
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#endif /* CONFIG_SOC_NRF52840 */
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#endif /* CONFIG_BT_CTLR_PHY_CODED */
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@ -1033,10 +1007,8 @@ void *radio_ccm_rx_pkt_set(struct ccm *ccm, u8_t phy, void *pkt)
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NRF_CCM->EVENTS_ENDCRYPT = 0;
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NRF_CCM->EVENTS_ERROR = 0;
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nrf_ppi_channel_endpoint_setup(HAL_TRIGGER_CRYPT_PPI,
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HAL_TRIGGER_CRYPT_PPI_EVT,
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HAL_TRIGGER_CRYPT_PPI_TASK);
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nrf_ppi_channels_enable(HAL_TRIGGER_CRYPT_PPI_ENABLE);
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hal_trigger_crypt_ppi_config();
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nrf_ppi_channels_enable(BIT(HAL_TRIGGER_CRYPT_PPI));
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nrf_ccm_task_trigger(NRF_CCM, NRF_CCM_TASK_KSGEN);
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@ -1113,10 +1085,8 @@ void radio_ar_configure(u32_t nirk, void *irk)
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radio_bc_configure(64);
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radio_bc_status_reset();
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nrf_ppi_channel_endpoint_setup(HAL_TRIGGER_AAR_PPI,
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HAL_TRIGGER_AAR_PPI_EVT,
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HAL_TRIGGER_AAR_PPI_TASK);
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nrf_ppi_channels_enable(HAL_TRIGGER_AAR_PPI_ENABLE);
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hal_trigger_aar_ppi_config();
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nrf_ppi_channels_enable(BIT(HAL_TRIGGER_AAR_PPI));
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}
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u32_t radio_ar_match_get(void)
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@ -5,12 +5,16 @@
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include "nrf_timer.h"
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#include <nrfx/hal/nrf_timer.h>
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#define HAL_RADIO_NS2US_CEIL(ns) ((ns + 999)/1000)
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#define HAL_RADIO_NS2US_ROUND(ns) ((ns + 500)/1000)
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#define EVENT_TIMER NRF_TIMER0
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/* Use the timer instance ID, not NRF_TIMERx directly, so that it can be checked
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* in radio_nrf5_ppi.h by the preprocessor.
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*/
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#define EVENT_TIMER_ID 0
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#define EVENT_TIMER _CONCAT(NRF_TIMER, EVENT_TIMER_ID)
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/* EVENTS_TIMER capture register used for sampling TIMER time-stamps. */
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#define HAL_EVENT_TIMER_SAMPLE_CC_OFFSET 3
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@ -181,8 +181,8 @@
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#if !defined(CONFIG_BT_CTLR_TIFS_HW)
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#if defined(CONFIG_BT_CTLR_SW_SWITCH_SINGLE_TIMER)
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#undef EVENT_TIMER
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#define EVENT_TIMER NRF_TIMER4
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#undef EVENT_TIMER_ID
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#define EVENT_TIMER_ID 4
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#define SW_SWITCH_TIMER EVENT_TIMER
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#define SW_SWITCH_TIMER_EVTS_COMP_BASE 4
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#else /* !CONFIG_BT_CTLR_SW_SWITCH_SINGLE_TIMER */
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@ -182,8 +182,8 @@
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#if !defined(CONFIG_BT_CTLR_TIFS_HW)
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#if defined(CONFIG_BT_CTLR_SW_SWITCH_SINGLE_TIMER)
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#undef EVENT_TIMER
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#define EVENT_TIMER NRF_TIMER4
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#undef EVENT_TIMER_ID
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#define EVENT_TIMER_ID 4
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#define SW_SWITCH_TIMER EVENT_TIMER
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#define SW_SWITCH_TIMER_EVTS_COMP_BASE 4
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#else /* !CONFIG_BT_CTLR_SW_SWITCH_SINGLE_TIMER */
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@ -339,8 +339,8 @@
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#if !defined(CONFIG_BT_CTLR_TIFS_HW)
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#if defined(CONFIG_BT_CTLR_SW_SWITCH_SINGLE_TIMER)
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#undef EVENT_TIMER
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#define EVENT_TIMER NRF_TIMER4
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#undef EVENT_TIMER_ID
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#define EVENT_TIMER_ID 4
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#define SW_SWITCH_TIMER EVENT_TIMER
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#define SW_SWITCH_TIMER_EVTS_COMP_BASE 3
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#define SW_SWITCH_TIMER_EVTS_COMP_S2_BASE 5
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@ -7,221 +7,307 @@
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#if defined(CONFIG_SOC_SERIES_NRF51X) || defined(CONFIG_SOC_COMPATIBLE_NRF52X)
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#include "nrf_ppi.h"
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#include <nrfx/hal/nrf_ppi.h>
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/* Enable Radio on Event Timer tick:
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/*******************************************************************************
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* Enable Radio on Event Timer tick:
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* wire the EVENT_TIMER EVENTS_COMPARE[0] event to RADIO TASKS_TXEN/RXEN task.
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*
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* Use the pre-programmed PPI channels if possible (if TIMER0 is used as the
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* EVENT_TIMER).
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*/
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#define HAL_RADIO_ENABLE_ON_TICK_PPI 0
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#define HAL_RADIO_ENABLE_ON_TICK_PPI_ENABLE \
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((PPI_CHENSET_CH0_Set << PPI_CHENSET_CH0_Pos) & PPI_CHENSET_CH0_Msk)
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#define HAL_RADIO_ENABLE_ON_TICK_PPI_DISABLE \
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((PPI_CHENCLR_CH0_Clear << PPI_CHENCLR_CH0_Pos) & PPI_CHENCLR_CH0_Msk)
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#define HAL_RADIO_ENABLE_ON_TICK_PPI_EVT \
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((u32_t)&(EVENT_TIMER->EVENTS_COMPARE[0]))
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#define HAL_RADIO_ENABLE_ON_TICK_PPI_TASK_TX \
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((u32_t)&(NRF_RADIO->TASKS_TXEN))
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#define HAL_RADIO_ENABLE_ON_TICK_PPI_TASK_RX \
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((u32_t)&(NRF_RADIO->TASKS_RXEN))
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#if (EVENT_TIMER_ID == 0)
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||||
|
||||
/* PPI channel 20 is pre-programmed with the following fixed settings:
|
||||
* EEP: TIMER0->EVENTS_COMPARE[0]
|
||||
* TEP: RADIO->TASKS_TXEN
|
||||
*/
|
||||
#define HAL_RADIO_ENABLE_TX_ON_TICK_PPI 20
|
||||
/* PPI channel 21 is pre-programmed with the following fixed settings:
|
||||
* EEP: TIMER0->EVENTS_COMPARE[0]
|
||||
* TEP: RADIO->TASKS_RXEN
|
||||
*/
|
||||
#define HAL_RADIO_ENABLE_RX_ON_TICK_PPI 21
|
||||
|
||||
static inline void hal_radio_enable_on_tick_ppi_config_and_enable(u8_t trx)
|
||||
{
|
||||
nrf_ppi_channel_endpoint_setup(HAL_RADIO_ENABLE_ON_TICK_PPI,
|
||||
HAL_RADIO_ENABLE_ON_TICK_PPI_EVT,
|
||||
(trx) ? HAL_RADIO_ENABLE_ON_TICK_PPI_TASK_TX :
|
||||
HAL_RADIO_ENABLE_ON_TICK_PPI_TASK_RX);
|
||||
nrf_ppi_channels_enable(HAL_RADIO_ENABLE_ON_TICK_PPI_ENABLE);
|
||||
/* No need to configure anything for the pre-programmed channels.
|
||||
* Just enable and disable them accordingly.
|
||||
*/
|
||||
nrf_ppi_channels_disable(
|
||||
trx ? BIT(HAL_RADIO_ENABLE_RX_ON_TICK_PPI)
|
||||
: BIT(HAL_RADIO_ENABLE_TX_ON_TICK_PPI));
|
||||
nrf_ppi_channels_enable(
|
||||
trx ? BIT(HAL_RADIO_ENABLE_TX_ON_TICK_PPI)
|
||||
: BIT(HAL_RADIO_ENABLE_RX_ON_TICK_PPI));
|
||||
}
|
||||
|
||||
/* Start event timer on RTC tick:
|
||||
#else
|
||||
|
||||
#define HAL_RADIO_ENABLE_ON_TICK_PPI 0
|
||||
#define HAL_RADIO_ENABLE_TX_ON_TICK_PPI HAL_RADIO_ENABLE_ON_TICK_PPI
|
||||
#define HAL_RADIO_ENABLE_RX_ON_TICK_PPI HAL_RADIO_ENABLE_ON_TICK_PPI
|
||||
|
||||
static inline void hal_radio_enable_on_tick_ppi_config_and_enable(u8_t trx)
|
||||
{
|
||||
u32_t event_address = (trx ? (u32_t)&(NRF_RADIO->TASKS_TXEN)
|
||||
: (u32_t)&(NRF_RADIO->TASKS_RXEN));
|
||||
nrf_ppi_channel_endpoint_setup(
|
||||
HAL_RADIO_ENABLE_ON_TICK_PPI,
|
||||
(u32_t)&(EVENT_TIMER->EVENTS_COMPARE[0]),
|
||||
event_address);
|
||||
nrf_ppi_channels_enable(BIT(HAL_RADIO_ENABLE_ON_TICK_PPI));
|
||||
}
|
||||
|
||||
#endif /* (EVENT_TIMER_ID == 0) */
|
||||
|
||||
/*******************************************************************************
|
||||
* Start event timer on RTC tick:
|
||||
* wire the RTC0 EVENTS_COMPARE[2] event to EVENT_TIMER TASKS_START task.
|
||||
*/
|
||||
#define HAL_EVENT_TIMER_START_PPI 1
|
||||
#define HAL_EVENT_TIMER_START_PPI_ENABLE \
|
||||
((PPI_CHENSET_CH1_Set << PPI_CHENSET_CH1_Pos) & PPI_CHENSET_CH1_Msk)
|
||||
#define HAL_EVENT_TIMER_START_PPI_DISABLE \
|
||||
((PPI_CHENCLR_CH1_Clear << PPI_CHENCLR_CH1_Pos) & PPI_CHENCLR_CH1_Msk)
|
||||
#define HAL_EVENT_TIMER_START_EVT \
|
||||
((u32_t)&(NRF_RTC0->EVENTS_COMPARE[2]))
|
||||
#define HAL_EVENT_TIMER_START_TASK \
|
||||
((u32_t)&(EVENT_TIMER->TASKS_START))
|
||||
|
||||
/* Capture event timer on Radio ready:
|
||||
static inline void hal_event_timer_start_ppi_config(void)
|
||||
{
|
||||
nrf_ppi_channel_endpoint_setup(
|
||||
HAL_EVENT_TIMER_START_PPI,
|
||||
(u32_t)&(NRF_RTC0->EVENTS_COMPARE[2]),
|
||||
(u32_t)&(EVENT_TIMER->TASKS_START));
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
* Capture event timer on Radio ready:
|
||||
* wire the RADIO EVENTS_READY event to the
|
||||
* EVENT_TIMER TASKS_CAPTURE[<radio ready timer>] task.
|
||||
*/
|
||||
#define HAL_RADIO_READY_TIME_CAPTURE_PPI 2
|
||||
#define HAL_RADIO_READY_TIME_CAPTURE_PPI_ENABLE \
|
||||
((PPI_CHENSET_CH2_Set << PPI_CHENSET_CH2_Pos) & PPI_CHENSET_CH2_Msk)
|
||||
#define HAL_RADIO_READY_TIME_CAPTURE_PPI_DISABLE \
|
||||
((PPI_CHENCLR_CH2_Clear << PPI_CHENCLR_CH2_Pos) & PPI_CHENCLR_CH2_Msk)
|
||||
#define HAL_RADIO_READY_TIME_CAPTURE_PPI_EVT \
|
||||
((u32_t)&(NRF_RADIO->EVENTS_READY))
|
||||
#define HAL_RADIO_READY_TIME_CAPTURE_PPI_TASK \
|
||||
((u32_t)&(EVENT_TIMER->TASKS_CAPTURE[0]))
|
||||
|
||||
/* Capture event timer on Address reception:
|
||||
static inline void hal_radio_ready_time_capture_ppi_config(void)
|
||||
{
|
||||
nrf_ppi_channel_endpoint_setup(
|
||||
HAL_RADIO_READY_TIME_CAPTURE_PPI,
|
||||
(u32_t)&(NRF_RADIO->EVENTS_READY),
|
||||
(u32_t)&(EVENT_TIMER->TASKS_CAPTURE[0]));
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
* Capture event timer on Address reception:
|
||||
* wire the RADIO EVENTS_ADDRESS event to the
|
||||
* EVENT_TIMER TASKS_CAPTURE[<address timer>] task.
|
||||
* EVENT_TIMER TASKS_CAPTURE[<address timer>] task.
|
||||
*
|
||||
* Use the pre-programmed PPI channel if possible (if TIMER0 is used as the
|
||||
* EVENT_TIMER).
|
||||
*/
|
||||
#define HAL_RADIO_RECV_TIMEOUT_CANCEL_PPI 3
|
||||
#define HAL_RADIO_RECV_TIMEOUT_CANCEL_PPI_ENABLE \
|
||||
((PPI_CHENSET_CH3_Set << PPI_CHENSET_CH3_Pos) & PPI_CHENSET_CH3_Msk)
|
||||
#define HAL_RADIO_RECV_TIMEOUT_CANCEL_PPI_DISABLE \
|
||||
((PPI_CHENCLR_CH3_Clear << PPI_CHENCLR_CH3_Pos) & PPI_CHENCLR_CH3_Msk)
|
||||
#define HAL_RADIO_RECV_TIMEOUT_CANCEL_PPI_EVT \
|
||||
((u32_t)&(NRF_RADIO->EVENTS_ADDRESS))
|
||||
#define HAL_RADIO_RECV_TIMEOUT_CANCEL_PPI_TASK \
|
||||
((u32_t)&(EVENT_TIMER->TASKS_CAPTURE[1]))
|
||||
#if (EVENT_TIMER_ID == 0)
|
||||
|
||||
/* Disable Radio on HCTO:
|
||||
/* PPI channel 26 is pre-programmed with the following fixed settings:
|
||||
* EEP: RADIO->EVENTS_ADDRESS
|
||||
* TEP: TIMER0->TASKS_CAPTURE[1]
|
||||
*/
|
||||
#define HAL_RADIO_RECV_TIMEOUT_CANCEL_PPI 26
|
||||
|
||||
static inline void hal_radio_recv_timeout_cancel_ppi_config(void)
|
||||
{
|
||||
/* No need to configure anything for the pre-programmed channel. */
|
||||
}
|
||||
|
||||
#else
|
||||
|
||||
#define HAL_RADIO_RECV_TIMEOUT_CANCEL_PPI 3
|
||||
|
||||
static inline void hal_radio_recv_timeout_cancel_ppi_config(void)
|
||||
{
|
||||
nrf_ppi_channel_endpoint_setup(
|
||||
HAL_RADIO_RECV_TIMEOUT_CANCEL_PPI,
|
||||
(u32_t)&(NRF_RADIO->EVENTS_ADDRESS),
|
||||
(u32_t)&(EVENT_TIMER->TASKS_CAPTURE[1]));
|
||||
}
|
||||
|
||||
#endif /* (EVENT_TIMER_ID == 0) */
|
||||
|
||||
/*******************************************************************************
|
||||
* Disable Radio on HCTO:
|
||||
* wire the EVENT_TIMER EVENTS_COMPARE[<HCTO timer>] event
|
||||
* to the RADIO TASKS_DISABLE task.
|
||||
*
|
||||
* Use the pre-programmed PPI channel if possible (if TIMER0 is used as the
|
||||
* EVENT_TIMER).
|
||||
*/
|
||||
#define HAL_RADIO_DISABLE_ON_HCTO_PPI 4
|
||||
#define HAL_RADIO_DISABLE_ON_HCTO_PPI_ENABLE \
|
||||
((PPI_CHENSET_CH4_Set << PPI_CHENSET_CH4_Pos) & PPI_CHENSET_CH4_Msk)
|
||||
#define HAL_RADIO_DISABLE_ON_HCTO_PPI_DISABLE \
|
||||
((PPI_CHENCLR_CH4_Clear << PPI_CHENCLR_CH4_Pos) & PPI_CHENCLR_CH4_Msk)
|
||||
#define HAL_RADIO_DISABLE_ON_HCTO_PPI_EVT \
|
||||
((u32_t)&(EVENT_TIMER->EVENTS_COMPARE[1]))
|
||||
#define HAL_RADIO_DISABLE_ON_HCTO_PPI_TASK \
|
||||
((u32_t)&(NRF_RADIO->TASKS_DISABLE))
|
||||
#if (EVENT_TIMER_ID == 0)
|
||||
|
||||
/* Capture event timer on Radio end:
|
||||
/* PPI channel 22 is pre-programmed with the following fixed settings:
|
||||
* EEP: TIMER0->EVENTS_COMPARE[1]
|
||||
* TEP: RADIO->TASKS_DISABLE
|
||||
*/
|
||||
#define HAL_RADIO_DISABLE_ON_HCTO_PPI 22
|
||||
|
||||
static inline void hal_radio_disable_on_hcto_ppi_config(void)
|
||||
{
|
||||
/* No need to configure anything for the pre-programmed channel. */
|
||||
}
|
||||
|
||||
#else
|
||||
|
||||
#define HAL_RADIO_DISABLE_ON_HCTO_PPI 4
|
||||
|
||||
static inline void hal_radio_disable_on_hcto_ppi_config(void)
|
||||
{
|
||||
nrf_ppi_channel_endpoint_setup(
|
||||
HAL_RADIO_DISABLE_ON_HCTO_PPI,
|
||||
(u32_t)&(EVENT_TIMER->EVENTS_COMPARE[1]),
|
||||
(u32_t)&(NRF_RADIO->TASKS_DISABLE));
|
||||
}
|
||||
|
||||
#endif /* (EVENT_TIMER_ID == 0) */
|
||||
|
||||
/*******************************************************************************
|
||||
* Capture event timer on Radio end:
|
||||
* wire the RADIO EVENTS_END event to the
|
||||
* EVENT_TIMER TASKS_CAPTURE[<radio end timer>] task.
|
||||
*
|
||||
* Use the pre-programmed PPI channel if possible (if TIMER0 is used as the
|
||||
* EVENT_TIMER).
|
||||
*/
|
||||
#if (EVENT_TIMER_ID == 0)
|
||||
|
||||
/* PPI channel 27 is pre-programmed with the following fixed settings:
|
||||
* EEP: RADIO->EVENTS_END
|
||||
* TEP: TIMER0->TASKS_CAPTURE[2]
|
||||
*/
|
||||
#define HAL_RADIO_END_TIME_CAPTURE_PPI 27
|
||||
|
||||
static inline void hal_radio_end_time_capture_ppi_config(void)
|
||||
{
|
||||
/* No need to configure anything for the pre-programmed channel. */
|
||||
}
|
||||
|
||||
#else
|
||||
|
||||
#define HAL_RADIO_END_TIME_CAPTURE_PPI 5
|
||||
#define HAL_RADIO_END_TIME_CAPTURE_PPI_ENABLE \
|
||||
((PPI_CHENSET_CH5_Set << PPI_CHENSET_CH5_Pos) & PPI_CHENSET_CH5_Msk)
|
||||
#define HAL_RADIO_END_TIME_CAPTURE_PPI_DISABLE \
|
||||
((PPI_CHENCLR_CH5_Clear << PPI_CHENCLR_CH5_Pos) & PPI_CHENCLR_CH5_Msk)
|
||||
#define HAL_RADIO_END_TIME_CAPTURE_PPI_EVT \
|
||||
((u32_t)&(NRF_RADIO->EVENTS_END))
|
||||
#define HAL_RADIO_END_TIME_CAPTURE_PPI_TASK \
|
||||
((u32_t)&(EVENT_TIMER->TASKS_CAPTURE[2]))
|
||||
|
||||
/* Trigger encryption task upon Address reception:
|
||||
static inline void hal_radio_end_time_capture_ppi_config(void)
|
||||
{
|
||||
nrf_ppi_channel_endpoint_setup(
|
||||
HAL_RADIO_END_TIME_CAPTURE_PPI,
|
||||
(u32_t)&(NRF_RADIO->EVENTS_END),
|
||||
(u32_t)&(EVENT_TIMER->TASKS_CAPTURE[2]));
|
||||
}
|
||||
|
||||
#endif /* (EVENT_TIMER_ID == 0) */
|
||||
|
||||
/*******************************************************************************
|
||||
* Trigger encryption task upon address reception:
|
||||
* wire the RADIO EVENTS_ADDRESS event to the CCM TASKS_CRYPT task.
|
||||
*
|
||||
* PPI channel 25 is pre-programmed with the following fixed settings:
|
||||
* EEP: RADIO->EVENTS_ADDRESS
|
||||
* TEP: CCM->TASKS_CRYPT
|
||||
*/
|
||||
#define HAL_TRIGGER_CRYPT_PPI 6
|
||||
#define HAL_TRIGGER_CRYPT_PPI_ENABLE \
|
||||
((PPI_CHENSET_CH6_Set << PPI_CHENSET_CH6_Pos) & PPI_CHENSET_CH6_Msk)
|
||||
#define HAL_TRIGGER_CRYPT_PPI_DISABLE \
|
||||
((PPI_CHENCLR_CH6_Clear << PPI_CHENCLR_CH6_Pos) & PPI_CHENCLR_CH6_Msk)
|
||||
#define HAL_TRIGGER_CRYPT_PPI_EVT \
|
||||
((u32_t)&(NRF_RADIO->EVENTS_ADDRESS))
|
||||
#define HAL_TRIGGER_CRYPT_PPI_TASK \
|
||||
((u32_t)&(NRF_CCM->TASKS_CRYPT))
|
||||
#define HAL_TRIGGER_CRYPT_PPI 25
|
||||
|
||||
/* Trigger automatic address resolution on Bit counter match:
|
||||
static inline void hal_trigger_crypt_ppi_config(void)
|
||||
{
|
||||
/* No need to configure anything for the pre-programmed channel. */
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
* Trigger automatic address resolution on Bit counter match:
|
||||
* wire the RADIO EVENTS_BCMATCH event to the AAR TASKS_START task.
|
||||
* Note that this PPI channel is shared with the encrypt triggering on Address
|
||||
* reception.
|
||||
*
|
||||
* PPI channel 23 is pre-programmed with the following fixed settings:
|
||||
* EEP: RADIO->EVENTS_BCMATCH
|
||||
* TEP: AAR->TASKS_START
|
||||
*/
|
||||
#define HAL_TRIGGER_AAR_PPI 6
|
||||
#define HAL_TRIGGER_AAR_PPI_ENABLE \
|
||||
((PPI_CHENSET_CH6_Set << PPI_CHENSET_CH6_Pos) & PPI_CHENSET_CH6_Msk)
|
||||
#define HAL_TRIGGER_AAR_PPI_DISABLE \
|
||||
((PPI_CHENCLR_CH6_Clear << PPI_CHENCLR_CH6_Pos) & PPI_CHENCLR_CH6_Msk)
|
||||
#define HAL_TRIGGER_AAR_PPI_EVT \
|
||||
((u32_t)&(NRF_RADIO->EVENTS_BCMATCH))
|
||||
#define HAL_TRIGGER_AAR_PPI_TASK \
|
||||
((u32_t)&(NRF_AAR->TASKS_START))
|
||||
#define HAL_TRIGGER_AAR_PPI 23
|
||||
|
||||
/* Trigger Radio Rate override upon Rateboost event. */
|
||||
static inline void hal_trigger_aar_ppi_config(void)
|
||||
{
|
||||
/* No need to configure anything for the pre-programmed channel. */
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
* Trigger Radio Rate override upon Rateboost event.
|
||||
*/
|
||||
#if defined(CONFIG_SOC_NRF52840)
|
||||
|
||||
#define HAL_TRIGGER_RATEOVERRIDE_PPI 13
|
||||
#define HAL_TRIGGER_RATEOVERRIDE_PPI_ENABLE \
|
||||
((PPI_CHENSET_CH13_Set << PPI_CHENSET_CH13_Pos) & PPI_CHENSET_CH13_Msk)
|
||||
#define HAL_TRIGGER_RATEOVERRIDE_PPI_DISABLE \
|
||||
((PPI_CHENCLR_CH13_Clear << PPI_CHENCLR_CH13_Pos) \
|
||||
& PPI_CHENCLR_CH13_Msk)
|
||||
#define HAL_TRIGGER_RATEOVERRIDE_PPI_REGISTER_EVT \
|
||||
NRF_PPI->CH[HAL_TRIGGER_RATEOVERRIDE_PPI].EEP
|
||||
#define HAL_TRIGGER_RATEOVERRIDE_PPI_EVT \
|
||||
((u32_t)&(NRF_RADIO->EVENTS_RATEBOOST))
|
||||
#define HAL_TRIGGER_RATEOVERRIDE_PPI_REGISTER_TASK \
|
||||
NRF_PPI->CH[HAL_TRIGGER_RATEOVERRIDE_PPI].TEP
|
||||
#define HAL_TRIGGER_RATEOVERRIDE_PPI_TASK \
|
||||
((u32_t)&(NRF_CCM->TASKS_RATEOVERRIDE))
|
||||
|
||||
static inline void hal_trigger_rateoverride_ppi_config(void)
|
||||
{
|
||||
nrf_ppi_channel_endpoint_setup(
|
||||
HAL_TRIGGER_RATEOVERRIDE_PPI,
|
||||
(u32_t)&(NRF_RADIO->EVENTS_RATEBOOST),
|
||||
(u32_t)&(NRF_CCM->TASKS_RATEOVERRIDE));
|
||||
}
|
||||
|
||||
#endif /* CONFIG_SOC_NRF52840 */
|
||||
|
||||
/******************************************************************************/
|
||||
#if defined(CONFIG_BT_CTLR_GPIO_PA_PIN) || defined(CONFIG_BT_CTLR_GPIO_LNA_PIN)
|
||||
|
||||
#define HAL_ENABLE_PALNA_PPI 14
|
||||
#define HAL_ENABLE_PALNA_PPI_ENABLE \
|
||||
((PPI_CHENSET_CH14_Set << PPI_CHENSET_CH14_Pos) & PPI_CHENSET_CH14_Msk)
|
||||
#define HAL_ENABLE_PALNA_PPI_DISABLE \
|
||||
((PPI_CHENCLR_CH14_Clear << PPI_CHENCLR_CH14_Pos) \
|
||||
& PPI_CHENCLR_CH14_Msk)
|
||||
#define HAL_ENABLE_PALNA_PPI_REGISTER_EVT \
|
||||
NRF_PPI->CH[HAL_ENABLE_PALNA_PPI].EEP
|
||||
#define HAL_ENABLE_PALNA_PPI_EVT \
|
||||
((u32_t)&(EVENT_TIMER->EVENTS_COMPARE[2]))
|
||||
#define HAL_ENABLE_PALNA_PPI_REGISTER_TASK \
|
||||
NRF_PPI->CH[HAL_ENABLE_PALNA_PPI].TEP
|
||||
#define HAL_ENABLE_PALNA_PPI_TASK \
|
||||
((u32_t)&(NRF_GPIOTE->TASKS_OUT[CONFIG_BT_CTLR_PA_LNA_GPIOTE_CHAN]))
|
||||
|
||||
static inline void hal_enable_palna_ppi_config(void)
|
||||
{
|
||||
nrf_ppi_channel_endpoint_setup(
|
||||
HAL_ENABLE_PALNA_PPI,
|
||||
(u32_t)&(EVENT_TIMER->EVENTS_COMPARE[2]),
|
||||
(u32_t)&(NRF_GPIOTE->TASKS_OUT[
|
||||
CONFIG_BT_CTLR_PA_LNA_GPIOTE_CHAN]));
|
||||
}
|
||||
|
||||
#define HAL_DISABLE_PALNA_PPI 15
|
||||
#define HAL_DISABLE_PALNA_PPI_ENABLE \
|
||||
((PPI_CHENSET_CH15_Set << PPI_CHENSET_CH15_Pos) & PPI_CHENSET_CH15_Msk)
|
||||
#define HAL_DISABLE_PALNA_PPI_DISABLE \
|
||||
((PPI_CHENCLR_CH15_Clear << PPI_CHENCLR_CH15_Pos) \
|
||||
& PPI_CHENCLR_CH15_Msk)
|
||||
#define HAL_DISABLE_PALNA_PPI_REGISTER_EVT \
|
||||
NRF_PPI->CH[HAL_DISABLE_PALNA_PPI].EEP
|
||||
#define HAL_DISABLE_PALNA_PPI_EVT \
|
||||
((u32_t)&(NRF_RADIO->EVENTS_DISABLED))
|
||||
#define HAL_DISABLE_PALNA_PPI_REGISTER_TASK \
|
||||
NRF_PPI->CH[HAL_DISABLE_PALNA_PPI].TEP
|
||||
#define HAL_DISABLE_PALNA_PPI_TASK \
|
||||
((u32_t)&(NRF_GPIOTE->TASKS_OUT[CONFIG_BT_CTLR_PA_LNA_GPIOTE_CHAN]))
|
||||
|
||||
static inline void hal_disable_palna_ppi_config(void)
|
||||
{
|
||||
nrf_ppi_channel_endpoint_setup(HAL_DISABLE_PALNA_PPI,
|
||||
(u32_t)&(NRF_RADIO->EVENTS_DISABLED),
|
||||
(u32_t)&(NRF_GPIOTE->TASKS_OUT[
|
||||
CONFIG_BT_CTLR_PA_LNA_GPIOTE_CHAN]));
|
||||
}
|
||||
|
||||
#endif /* CONFIG_BT_CTLR_GPIO_PA_PIN || CONFIG_BT_CTLR_GPIO_LNA_PIN */
|
||||
|
||||
/******************************************************************************/
|
||||
#if !defined(CONFIG_BT_CTLR_TIFS_HW)
|
||||
/* PPI setup used for SW-based auto-switching during TIFS. */
|
||||
|
||||
#if !defined(CONFIG_BT_CTLR_SW_SWITCH_SINGLE_TIMER)
|
||||
|
||||
/* Clear SW-switch timer on packet end:
|
||||
* wire the RADIO EVENTS_END event to SW_SWITCH_TIMER TASKS_CLEAR task.
|
||||
*
|
||||
* Note: this PPI is not needed if we use a single TIMER instance in radio.c
|
||||
*/
|
||||
#define HAL_SW_SWITCH_TIMER_CLEAR_PPI 7
|
||||
#define HAL_SW_SWITCH_TIMER_CLEAR_PPI_ENABLE \
|
||||
((PPI_CHENSET_CH7_Set << PPI_CHENSET_CH7_Pos) & PPI_CHENSET_CH7_Msk)
|
||||
#define HAL_SW_SWITCH_TIMER_CLEAR_PPI_DISABLE \
|
||||
((PPI_CHENCLR_CH7_Clear << PPI_CHENCLR_CH7_Pos) & PPI_CHENCLR_CH7_Msk)
|
||||
|
||||
static inline void hal_sw_switch_timer_clear_ppi_config(void)
|
||||
{
|
||||
nrf_ppi_channel_endpoint_setup(
|
||||
HAL_SW_SWITCH_TIMER_CLEAR_PPI,
|
||||
(u32_t)&(NRF_RADIO->EVENTS_END),
|
||||
(u32_t)&(SW_SWITCH_TIMER->TASKS_CLEAR));
|
||||
}
|
||||
|
||||
#else /* !CONFIG_BT_CTLR_SW_SWITCH_SINGLE_TIMER */
|
||||
|
||||
/* Clear event timer (sw-switch timer) on Radio end:
|
||||
* wire the RADIO EVENTS_END event to the
|
||||
* EVENT_TIMER TASKS_CLEAR task.
|
||||
*
|
||||
* Note: in nRF52X PPI 5 is forked for both capturing and clearing timer
|
||||
* on RADIO EVENTS_END.
|
||||
* Note: in nRF52X this PPI channel is forked for both capturing and clearing
|
||||
* timer on RADIO EVENTS_END.
|
||||
*/
|
||||
#define HAL_SW_SWITCH_TIMER_CLEAR_PPI 5
|
||||
#define HAL_SW_SWITCH_TIMER_CLEAR_PPI_ENABLE \
|
||||
((PPI_CHENSET_CH5_Set << PPI_CHENSET_CH5_Pos) & PPI_CHENSET_CH5_Msk)
|
||||
#define HAL_SW_SWITCH_TIMER_CLEAR_PPI_DISABLE \
|
||||
((PPI_CHENCLR_CH5_Clear << PPI_CHENCLR_CH5_Pos) & PPI_CHENCLR_CH5_Msk)
|
||||
#endif /* !CONFIG_BT_CTLR_SW_SWITCH_SINGLE_TIMER */
|
||||
#define HAL_SW_SWITCH_TIMER_CLEAR_PPI_REGISTER_EVT \
|
||||
NRF_PPI->CH[HAL_SW_SWITCH_TIMER_CLEAR_PPI].EEP
|
||||
#define HAL_SW_SWITCH_TIMER_CLEAR_PPI_EVT \
|
||||
((u32_t)&(NRF_RADIO->EVENTS_END))
|
||||
#if !defined(CONFIG_BT_CTLR_SW_SWITCH_SINGLE_TIMER)
|
||||
#define HAL_SW_SWITCH_TIMER_CLEAR_PPI_REGISTER_TASK \
|
||||
NRF_PPI->CH[HAL_SW_SWITCH_TIMER_CLEAR_PPI].TEP
|
||||
#else /* !CONFIG_BT_CTLR_SW_SWITCH_SINGLE_TIMER */
|
||||
#define HAL_SW_SWITCH_TIMER_CLEAR_PPI_REGISTER_TASK \
|
||||
NRF_PPI->FORK[HAL_SW_SWITCH_TIMER_CLEAR_PPI].TEP
|
||||
#define HAL_SW_SWITCH_TIMER_CLEAR_PPI HAL_RADIO_END_TIME_CAPTURE_PPI
|
||||
|
||||
static inline void hal_sw_switch_timer_clear_ppi_config(void)
|
||||
{
|
||||
nrf_ppi_fork_endpoint_setup(
|
||||
HAL_RADIO_END_TIME_CAPTURE_PPI,
|
||||
(u32_t)&(SW_SWITCH_TIMER->TASKS_CLEAR));
|
||||
}
|
||||
|
||||
#endif /* !CONFIG_BT_CTLR_SW_SWITCH_SINGLE_TIMER */
|
||||
#define HAL_SW_SWITCH_TIMER_CLEAR_PPI_TASK \
|
||||
((u32_t)&(SW_SWITCH_TIMER->TASKS_CLEAR))
|
||||
|
||||
/* The 2 adjacent PPI groups used for implementing SW_SWITCH_TIMER-based
|
||||
* auto-switch for TIFS. 'index' must be 0 or 1.
|
||||
|
|
@ -264,11 +350,6 @@ static inline void hal_radio_enable_on_tick_ppi_config_and_enable(u8_t trx)
|
|||
* 2 adjacent PPI groups are used for this wiring. 'index' must be 0 or 1.
|
||||
*/
|
||||
#define HAL_SW_SWITCH_GROUP_TASK_ENABLE_PPI 10
|
||||
#define HAL_SW_SWITCH_GROUP_TASK_ENABLE_PPI_ENABLE \
|
||||
((PPI_CHENSET_CH10_Set << PPI_CHENSET_CH10_Pos) & PPI_CHENSET_CH10_Msk)
|
||||
#define HAL_SW_SWITCH_GROUP_TASK_ENABLE_PPI_DISABLE \
|
||||
((PPI_CHENCLR_CH10_Clear << PPI_CHENCLR_CH10_Pos) \
|
||||
& PPI_CHENCLR_CH10_Msk)
|
||||
#define HAL_SW_SWITCH_GROUP_TASK_ENABLE_PPI_EVT \
|
||||
((u32_t)&(NRF_RADIO->EVENTS_END))
|
||||
#define HAL_SW_SWITCH_GROUP_TASK_ENABLE_PPI_TASK(index) \
|
||||
|
|
@ -318,7 +399,6 @@ static inline void hal_radio_rxen_on_sw_switch(u8_t ppi)
|
|||
#if defined(CONFIG_SOC_NRF52840)
|
||||
/* Wire the SW SWITCH TIMER EVENTS_COMPARE[<cc_offset>] event
|
||||
* to RADIO TASKS_TXEN/RXEN task.
|
||||
* 2 adjacent PPIs (16 & 17) are used for this wiring; <index> must be 0 or 1.
|
||||
*/
|
||||
#define HAL_SW_SWITCH_RADIO_ENABLE_S2_PPI 16
|
||||
#define HAL_SW_SWITCH_RADIO_ENABLE_S2_PPI_INCLUDE \
|
||||
|
|
@ -330,11 +410,6 @@ static inline void hal_radio_rxen_on_sw_switch(u8_t ppi)
|
|||
* wire the RADIO EVENTS_RATEBOOST event to SW_SWITCH_TIMER TASKS_CAPTURE task.
|
||||
*/
|
||||
#define HAL_SW_SWITCH_TIMER_S8_DISABLE_PPI 17
|
||||
#define HAL_SW_SWITCH_TIMER_S8_DISABLE_PPI_ENABLE \
|
||||
((PPI_CHENSET_CH18_Set << PPI_CHENSET_CH18_Pos) & PPI_CHENSET_CH18_Msk)
|
||||
#define HAL_SW_SWITCH_TIMER_S8_DISABLE_PPI_DISABLE \
|
||||
((PPI_CHENCLR_CH18_Clear << PPI_CHENCLR_CH18_Pos) \
|
||||
& PPI_CHENCLR_CH18_Msk)
|
||||
#define HAL_SW_SWITCH_TIMER_S8_DISABLE_PPI_REGISTER_EVT \
|
||||
NRF_PPI->CH[HAL_SW_SWITCH_TIMER_S8_DISABLE_PPI].EEP
|
||||
#define HAL_SW_SWITCH_TIMER_S8_DISABLE_PPI_EVT \
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue