We are arbitrarily setting a value to PS after power gates and
losing valid information like OWB, CALLINC and INTLEVEL.
We need to properly save/restore them to avoid possible wrong behavior.
Signed-off-by: Flavio Ceolin <flavio.ceolin@intel.com>
When exiting power gated state, call the CPU start function
passed to arch_start_cpu().
Signed-off-by: Rander Wang <rander.wang@intel.com>
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
Use 'switch' to emphasise that we're handling different values of
'state' in pm_state_set().
Signed-off-by: Guennadi Liakhovetski <guennadi.liakhovetski@linux.intel.com>
'ret' in pm_state_set() is always set before it's used, no need to
initialise it.
Signed-off-by: Guennadi Liakhovetski <guennadi.liakhovetski@linux.intel.com>
This patch introduces power management for the HOST (HST) domain within
the Intel ADSP ACE IP. It adds macros to access the node identifier and
device pointer for the HST power domain and integrates power management
calls into the system initialization and power state transition
functions.
The patch ensures that power gating of the HST domain is prevented when
the primary core of the audio DSP is active. Preventing power gating is
crucial for maintaining the functionality of the HST domain while the
primary DSP core is performing critical tasks.
Signed-off-by: Tomasz Leman <tomasz.m.leman@intel.com>
This patch enables DSP clock gating for ACE platforms. By default, clock
gating is blocked by the firmware in the hardware configuration. If
CONFIG_ADSP_IDLE_CLOCK_GATING is enabled, this prevent is not active and
clock can be gated when core is in idle state. WIth this option disabled
clock gating will only be enabled in hardware during power gating.
Signed-off-by: Tomasz Leman <tomasz.m.leman@intel.com>
Use WAIT_FOR to wait for core power changes to be reflected
in status registers. If core power state does not complete in
10ms, k_panic() is raised.
Signed-off-by: Kai Vehmanen <kai.vehmanen@linux.intel.com>
With gcc from the zephyr sdk and -Wold-style-declaration is giving this
output:
zephyr/arch/arm/core/aarch32/cortex_a_r/fault.c:101:1: warning:
'inline' is not at beginning of declaration [-Wold-style-declaration]
101 | static void ALWAYS_INLINE
z_arm_fpu_caller_save(struct __fpu_sf *fpu)
| ^~~~~~
I searched to all of the source code to find these further occurances
where inline is not at the beginning of a function declaration.
Signed-off-by: Florian La Roche <Florian.LaRoche@gmail.com>
Add an option to control whether or not hpsram banks should
be switched off during the power down. This is particular useful
when running tests because we don't want to lose the contents
of the memory window before we capture it.
Signed-off-by: Flavio Ceolin <flavio.ceolin@intel.com>
Remove unnecessary __weak attribute from power management functions.
These functions are now defined once, globally, and mandatory for
systems that support CONFIG_PM.
Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
Instead of relying on direct memory access via structs to
control CPU power and status, using inline functions instead
to hide the details. This makes reading the common code a bit
cleaner.
The function names are generic and not architecture or
platform specific, in an attempt to ease future arch or
platform additions with code reuse. Or else we would need to
rename these.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
After exiting D3 state if IMR context save is enabled, IDC interrupt
must be re-enabled again for all cores.
Signed-off-by: Serhiy Katsyuba <serhiy.katsyuba@intel.com>
Exiting idle state requires to reinitialize all memory window
instances to flush the cached memory.
Added function that calls initialization of devices during runtime.
Signed-off-by: Andrey Borisovich <andrey.borisovich@intel.com>
Generic header for system clock allows to define a sys_clock_idle_exit
function for the clock implementation.
Implemented the function in the intel_adsp_timer to reinitialize
device driver after the idle exit state.
Signed-off-by: Andrey Borisovich <andrey.borisovich@intel.com>
This patch moves cache flush/invalidation to section executed only when
IMR context saving is enabled. If this option is disabled no FW context
is stored so any lost data doesn't matter.
Signed-off-by: Tomasz Leman <tomasz.m.leman@intel.com>
Masking out all interrupt during power state transition and restoring
them after is now common thing for all power states. No need to
duplicate code.
Signed-off-by: Tomasz Leman <tomasz.m.leman@intel.com>
Reusing primary core context save/restore flow for purpose of secondary
core D0 -> D3 -> D0 transitions. If core is re-enabled we use
dsp_restore_vector as the FW entry point.
Signed-off-by: Tomasz Leman <tomasz.m.leman@intel.com>
This patch is preparing cpu context save and restore code so it can be
later used by the multiple cores.
Signed-off-by: Tomasz Leman <tomasz.m.leman@intel.com>
This patch replace temporary stack of the restore vector with interrupt
stack to reduce memory usage. Additionally we can assign seprate stack
for each core. This will allow to reuse this vector for secondary cores.
Signed-off-by: Tomasz Leman <tomasz.m.leman@intel.com>
Reusing existing code during CPU init at power gating exit.
Additional changes:
- replacing magic value for memctl and atomctl with more readable
definitions,
- using dedicated macros in place of asm inlines.
Signed-off-by: Tomasz Leman <tomasz.m.leman@intel.com>
The watchdog is controlled by ll-scheduler and should not be resumed when
a core is bringing up. Watchdog pause control code was removed.
Signed-off-by: Adrian Warecki <adrian.warecki@intel.com>
Temporary re-enabling interrupts before going to waiti. Right now
secondary cores don't have proper context restore flow and after leaving
D3 state core will return here and stuck. This is temporary workaround.
Signed-off-by: Tomasz Leman <tomasz.m.leman@intel.com>
This patch is moving common power configuration code outside of the
section only for the primary core. This should be enabled for all cores
and it was put there probably by mistake.
Signed-off-by: Tomasz Leman <tomasz.m.leman@intel.com>
The code used the name DFDSPBRCP referring to the DSP Boot / Recovery
Capability Pointer register from DSP Subsystem Capability / Status
Registers range. The address used, however, pointed to DSP Core Shim
(DSPCS) registers block. Changed define names to not be misleading.
Signed-off-by: Adrian Warecki <adrian.warecki@intel.com>
If defined(CONFIG_ASSERT) and !defined(CONFIG_ADSP_IMR_CONTEXT_SAVE),
build will fail as symbol "global_imr_ram_storage" is not defined.
Link: https://github.com/thesofproject/sof/issues/6896
Signed-off-by: Kai Vehmanen <kai.vehmanen@linux.intel.com>
This patch makes IMR context save an option that can be enabled. By
default FW, after D3 state transition, will be boot using normal flow.
Signed-off-by: Tomasz Leman <tomasz.m.leman@intel.com>
SOF compilation is sensitive to compilation warnings
Some simple and neutral changes to avoid them
Signed-off-by: Marcin Szkudlinski <marcin.szkudlinski@intel.com>
IMR save and restore context is a flow implemented for ACE
move boot specific procedures to ace subdir
Signed-off-by: Marcin Szkudlinski <marcin.szkudlinski@intel.com>
Context save is saving whole memory to persistent
memory area, than turning off memory and CPU
Context restore is a modified boot flow, where
the previously saved context is restored
Signed-off-by: Marcin Szkudlinski <marcin.szkudlinski@intel.com>
The restore vector after power gating was configuring the MEMCTL register
incorrectly. This caused an FW crash during the cache prefetch.
Additionally, since lp sram cache issue was fixed, xtensa hal function
can be replace with zephyr equivalent.
Signed-off-by: Tomasz Leman <tomasz.m.leman@intel.com>
File still not being removed due to out-of-tree usage. We will drop it
once the external code has stopped referencing it.
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Split the defines based on domain and cleanup ace_v1x-regs.h so we can
finally remove it and stop include soc specific headers across the tree.
Future generations of this family will be able to use the same naming
scheme without having to use the version name in the file name.
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
If the target is built without CONFIG_PM this stack is not
used and does not need to be defined.
Signed-off-by: Flavio Ceolin <flavio.ceolin@intel.com>
