intel_adsp/ace: power: Restore PS after power gate
We are arbitrarily setting a value to PS after power gates and losing valid information like OWB, CALLINC and INTLEVEL. We need to properly save/restore them to avoid possible wrong behavior. Signed-off-by: Flavio Ceolin <flavio.ceolin@intel.com>
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1 changed files with 8 additions and 0 deletions
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@ -111,6 +111,7 @@ struct core_state {
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uint32_t excsave3;
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uint32_t thread_ptr;
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uint32_t intenable;
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uint32_t ps;
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uint32_t bctl;
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};
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@ -127,6 +128,7 @@ struct lpsram_header {
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static ALWAYS_INLINE void _save_core_context(uint32_t core_id)
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{
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core_desc[core_id].ps = XTENSA_RSR("PS");
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core_desc[core_id].vecbase = XTENSA_RSR("VECBASE");
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core_desc[core_id].excsave2 = XTENSA_RSR("EXCSAVE2");
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core_desc[core_id].excsave3 = XTENSA_RSR("EXCSAVE3");
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@ -140,6 +142,7 @@ static ALWAYS_INLINE void _restore_core_context(void)
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{
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uint32_t core_id = arch_proc_id();
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XTENSA_WSR("PS", core_desc[core_id].ps);
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XTENSA_WSR("VECBASE", core_desc[core_id].vecbase);
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XTENSA_WSR("EXCSAVE2", core_desc[core_id].excsave2);
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XTENSA_WSR("EXCSAVE3", core_desc[core_id].excsave3);
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@ -404,6 +407,11 @@ void pm_state_exit_post_ops(enum pm_state state, uint8_t substate_id)
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}
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z_xt_ints_on(core_desc[cpu].intenable);
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/* We don't have the key used to lock interruptions here.
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* Just set PS.INTLEVEL to 0.
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*/
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__asm__ volatile ("rsil a2, 0");
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}
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#endif /* CONFIG_PM */
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