Commit graph

144 commits

Author SHA1 Message Date
Sylvio Alves
213142db21 soc: espressif: riscv: disable local isr location
Disable support to local ISR declaration on Espressif SoCs.
Code relocation is not yet supported, causing build fail.

Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
2025-06-13 15:40:09 -07:00
Marcio Ribeiro
77c350c149 soc: esp32: virtual e-fuses support
Adds support for virtual e-fuses on esp32 socs

Signed-off-by: Marcio Ribeiro <marcio.ribeiro@espressif.com>
2025-06-04 17:00:20 +02:00
Raffael Rostagno
588c2e66e9 soc: esp32c6: Fix sleep routine
PMU related functions need to be located in IRAM when sleep
process is triggered, as cache is disabled past a certain point
in the execution of the sleep process.

Signed-off-by: Raffael Rostagno <raffael.rostagno@espressif.com>
2025-05-30 16:34:48 +02:00
Daniel Leung
1f21bb9003 soc: esp32: include ksched.h in esp32-mp.c
esp32-mp.c calls z_sched_ipi() so it needs to include ksched.h,
as it is no longer included via kernel.h after removal of
kernel/internal/smp.h.

Signed-off-by: Daniel Leung <daniel.leung@intel.com>
2025-05-06 20:36:26 +02:00
Lucas Tamborrino
232e2c5a3c drivers: uart: espressif: Add LP UART driver
Add LP UART driver for LP Core

Signed-off-by: Lucas Tamborrino <lucas.tamborrino@espressif.com>
2025-04-11 13:34:17 +02:00
Lucas Tamborrino
0b79b47811 soc: espressif: Filter LP Core from esptool command
Filter LP Core from esptool post build commands

Signed-off-by: Lucas Tamborrino <lucas.tamborrino@espressif.com>
2025-04-11 13:34:17 +02:00
Marek Matej
f10e7b8395 soc: espressif: esp32: Allow DRAM1 to use for .noinit
Add config to relocate the .noinit section to DRAM1 region.
Remove unused config.

Signed-off-by: Marek Matej <marek.matej@espressif.com>
2025-04-07 07:27:23 +02:00
Sylvio Alves
ac0705d59b soc: espressif: update restart procedure
Use esp_restart call to guarantee and registered
shutdown handlers will be triggered before rebooting.
This guarantees that subsystems like Wi-Fi and BLE
will deinit correctly.

Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
2025-04-05 11:02:13 +02:00
Sylvio Alves
9857f114f8 linker: esp32: move regi2c_ctrl to iram
This prevents boot lock up due to critical sections
calls during bootloader stage.

Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
2025-04-03 00:03:56 +02:00
Raffael Rostagno
eb606a8e7d soc: esp32: Update IRQ config for shared allocator
Update IRQ handling related files to unify interrupt controller
between Xtensa and RISCV devices.

Signed-off-by: Raffael Rostagno <raffael.rostagno@espressif.com>
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
2025-04-02 19:02:27 +02:00
Lucas Tamborrino
c6f84d0ba2 boards: espressif: esp32c6: Add LP Core board support
Add ULP Coprocessor board support for C6.
This requires a change in the board qualifier depending on the build
target.
Update esp32c6 overlay and configuration files to the proper name.

Signed-off-by: Lucas Tamborrino <lucas.tamborrino@espressif.com>
2025-03-21 17:05:20 +01:00
Lucas Tamborrino
0b9e4e013a soc: espressif: esp32c6: Add LP Core
Add ULP Coprocessor support for ESP32C6.

Signed-off-by: Lucas Tamborrino <lucas.tamborrino@espressif.com>
2025-03-21 17:05:20 +01:00
Anas Nashif
f29ae72d79 kernel: rename 'dumb' scheduler and simply call it 'simple'
Improve naming of the scheduler and call it what it is: simple. Using
'dumb' for the default scheduler algorithm in Zephyr is a bad idea.

Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2025-03-15 00:34:58 +01:00
Sylvio Alves
f22de9733b soc: esp32: riscv: fix interrupt allocator
Current interrupt allocator is not taking into account
reserved areas. In case of esp32c6, Wi-Fi isn't properly
configured, causing instability or even non-functional feature.
This adds the reserved area ranges for all risc-v based SoC and
unify the slot finding based on interrupt source.

Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
2025-03-06 08:35:29 +00:00
Sylvio Alves
5729552360 soc: esp32: fix flash QIO mode boot
Make sure QIO mode calls are not in flash, otherwise
it will fail during bootloader/flash init.

Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
2025-03-05 00:15:33 +00:00
Sylvio Alves
b8c710d6c4 soc: espressif: fix chip revision reading
Make sure chip revision reading returns real value
for some especific chip revision, which is currently
failing.

Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
2025-03-04 18:26:34 +00:00
Raffael Rostagno
40823be8b7 runners: esp32: Fix board arguments
Fix board arguments to properly build runners.yaml and
set esp-monitor-baud.

Signed-off-by: Raffael Rostagno <raffael.rostagno@espressif.com>
2025-02-27 23:19:20 +00:00
Sylvio Alves
1903a8f415 soc: espressif: fix optimization flag boot fault
When DEBUG_OPTIMIZATION or NO_OPTIMIZATION is
enabled, efuse reading fails during bootloader start.
Move those calls into IRAM area so that reading when
cache is disabled works without any faults.

In HAL side, we need to use low level calls to read
CPU id instead of Zephyr's default one.

Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
2025-02-26 07:41:31 +01:00
Marek Matej
d13fae97e4 soc: espressif: Fix psram0 node size and smh heap size calculation
Fixing multiple things related to psram usage:
- fix conflicting psram0 dts node for all ESP32 SiP and SoC.
- fix dcache and icache area used in psram mapping.
- fix smh spiram heap allocations.
- add `espressif,esp32-psram` compatible to set psram0 size in dts.

Signed-off-by: Marek Matej <marek.matej@espressif.com>
2025-02-25 07:56:19 +01:00
Sylvio Alves
3c1e11c003 linker: espressif: clean up mcuboot iram entries
As a result of flash initialization improvements
and fixes, some of the mcuboot linker entries
are no longer necessary.

Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
2025-02-14 17:07:40 +01:00
Sylvio Alves
69a6736ba1 soc: espressif: use commom board runner among chips
Currently, each SoC has its own CMakeLists.txt file
to handle esp32 runner.
This PR merged it all in a common file and fixes
missing configuration such as flashing frequency,
mode and size.

Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
2025-02-14 17:07:40 +01:00
Sylvio Alves
36705c4f8e soc: espressif: remove vddio boost during boot
Removes the VDDSDIO control during boot for some SoCs.
Only ESP32 allows managing such configuration during
initialization.

Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
2025-02-14 17:07:40 +01:00
Sylvio Alves
e36d702acd soc: espressif: move code start prior hw init
Make sure vector table and BSS clean up
is performed pior hardware initialization.

Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
2025-02-14 17:07:40 +01:00
Marek Matej
9e49bbf179 soc: espressif: esp32s3: Add files to support AMP
Update to support APP_CPU flash access.

- fix the map_rom_segment so it can be used in other context
- add IROM and DROM region size in Kconfig
- update the memory.h by using dts records
- fix the appcpu ld file to support flash

Signed-off-by: Marek Matej <marek.matej@espressif.com>
2025-02-12 20:25:48 +01:00
Sylvio Alves
10860ecbba soc: espressif: enable Wi-Fi/Bluetooth SW coexistence mgmt
Update and enable Wi-Fi/Bluetooth software coexistence management.
This improves package handling and is recommended to be used
in high traffic scenarios.

Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
2025-02-12 20:20:11 +01:00
Sylvio Alves
b426e0925d soc: esp32c2: add ECO4 revision entry
Allows using proper rom functions when ECO4 module
is used.

Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
2025-02-11 22:05:04 +01:00
Jamie McCrae
a0d62db81f soc: espressif: Move MAIN_STACK_SIZE to defconfig files
Moves this Kconfig value to be the default in the
Kconfig.defconfig files

Signed-off-by: Jamie McCrae <jamie.mccrae@nordicsemi.no>
2025-02-11 10:12:23 +01:00
Sylvio Alves
a0bdafb021 espressif: add console and RTC kconfig entries
Add hidden console and RTC configurations used in hal
to common SoC folder.

Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
2025-02-10 19:05:40 +01:00
Marek Matej
6e6ab2f8ab soc: espressif: Remove ESP heap and use heap adapter
Remove ESP heap from the sources. System heap is default heap.
Use heap adapter layer to configure used heap.
Use MEM_POOL memory request config to Wi-Fi and Bluetooth drivers.
Update the Wi-Fi and BLE memory needs.

Signed-off-by: Marek Matej <marek.matej@espressif.com>
2025-02-05 17:49:54 +01:00
Marcio Ribeiro
c3b53d0fa3 soc: esp32xx: makes esp_console_init() calling conditional
Makes the esp_console_init() calling during hardware initialization
conditioned to CONFIG_ESP_CONSOLE

Signed-off-by: Marcio Ribeiro <marcio.ribeiro@espressif.com>
2025-01-30 16:21:13 +01:00
Sylvio Alves
4456ecc0a3 soc: esp32xx: remove unused kconfig entry
ESP_HEAP_SEARCH_ALL_REGIONS kconfig entry is not
used and can be totally removed.

Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
2025-01-23 13:45:31 +01:00
Sylvio Alves
3d3217ea6a hci: esp32: remove deprecated symbol
Make sure HAS_BT_CTLR is used instead
of deprecated BT_CTLR symbol.

Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
2025-01-23 00:13:17 +01:00
Sylvio Alves
6a60927cac soc: espressif: enable custom bluetooth options
In order to allow Espressif boards to change BLE TX power,
BT_CTRL needs to be enabled.

Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
2025-01-19 19:21:52 +01:00
Marek Matej
dd6f176e73 soc: espressif: Allow noinit segment in SPIRAM
Add SPIRAM noinit output sections on related targets so the user can
allocate variables with macros EXT_RAM_BSS_ATTR and EXT_RAM_NOINIT_ATTR.

Signed-off-by: Marek Matej <marek.matej@espressif.com>
2025-01-14 13:30:14 +01:00
Marek Matej
d276cf753f soc: espressif: Extend the program header
Add new fields to the `esp_image_load_header_t`

* provide IROM and DROM fields to fix debugging features
* extend the header to up to 96 Bytes for future use

Signed-off-by: Marek Matej <marek.matej@espressif.com>
2025-01-14 00:01:20 +01:00
Sylvio Alves
5d05e28fce soc: espressif: keep RTC data after deep-sleep
This PR includes changes in all Espressif's SoCs to enable
keeping data in RTC memory after deep-sleep.

Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
2025-01-10 18:57:46 +01:00
Nicolas Pitre
46aa6717ff Revert "arch: deprecate _current"
Mostly a revert of commit b1def7145f ("arch: deprecate `_current`").

This commit was part of PR #80716 whose initial purpose was about providing
an architecture specific optimization for _current. The actual deprecation
was sneaked in later on without proper discussion.

The Zephyr core always used _current before and that was fine. It is quite
prevalent as well and the alternative is proving rather verbose.
Furthermore, as a concept, the "current thread" is not something that is
necessarily architecture specific. Therefore the primary abstraction
should not carry the arch_ prefix.

Hence this revert.

Signed-off-by: Nicolas Pitre <npitre@baylibre.com>
2025-01-10 07:49:08 +01:00
Sylvio Alves
1681c7e317 soc: esp32: fix appcpu register access
Build is failing due to wrong calls to appcpu
stall and clock gating. This fixes it
by using proper registers.

Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
2024-12-25 03:37:39 +01:00
Marek Matej
930000d3b3 soc: espressif: Rename common/psram.c
Rename psram.c -> esp_psram.c to align with the naming conventions.

Signed-off-by: Marek Matej <marek.matej@espressif.com>
2024-12-16 20:49:10 +01:00
Marek Matej
e62f6651a0 soc: esp32s3: Fix WiFi allocation to SPIRAM
Fix the allocations if the SPIRAM and WiFi alloc to SPIRAM
are both enabled.

Signed-off-by: Marek Matej <marek.matej@espressif.com>
2024-12-16 20:49:10 +01:00
Marek Matej
cf73e90acd soc: esp32: Fix WiFi allocations to SPIRAM
Fix allocations of large buffers if SPIRAM and WiFi alloc
to SPIRAM are both enabled.

Signed-off-by: Marek Matej <marek.matej@espressif.com>
2024-12-16 20:49:10 +01:00
Marcio Ribeiro
cdbb1ddbad soc: esp32: change SRAM1_IRAM_START macro definition
Changes the SRAM1_IRAM_START macro definition for:
- esp32c2
- esp32c3

Signed-off-by: Marcio Ribeiro <marcio.ribeiro@espressif.com>
2024-12-12 19:59:44 +01:00
Marek Matej
c69ecabc7a soc: esp32s3: update APPCPU code
Updates for AMP targets

- use common AMP Kconfig
- update APPCPU linker script
- place AMP common area in the reserved space

Signed-off-by: Marek Matej <marek.matej@espressif.com>
2024-12-12 11:38:22 +01:00
Marek Matej
322ab2a86e soc: esp32: fixes and updates for AMP
Multiple AMP related updates:

- use common AMP Kconfig
- rework the APPCPU linker script
- use MCUboot image format for APPCPU image
- fix multi-processing startup code

Signed-off-by: Marek Matej <marek.matej@espressif.com>
2024-12-12 11:38:22 +01:00
Sylvio Alves
fc7cacc983 soc: esp32: fix smp_log usage
smp_log usage should be only used when SMP is enabled.
This is currently causing build issues after the fix
provided by #82377

Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
2024-12-09 22:05:23 +00:00
Marcio Ribeiro
7f13961884 soc: esp32: replace hard-coded addresses and sizes by DT macros
Replaces hard-coded memory addresses and sizes with macros that retrieve
such values from the device tree.

Signed-off-by: Marcio Ribeiro <marcio.ribeiro@espressif.com>
2024-12-07 11:02:46 +01:00
Arif Balik
3b5003de18 soc: espressif: fix missing spinlock definition
This definition is deleted in the follwoing commit;
8233b70
as a part of "cleanup", however this definition is
used by smp_log

Signed-off-by: Arif Balik <arifbalik@outlook.com>
2024-12-03 23:29:46 +00:00
Jamie McCrae
d7d636d1f2 soc: expressif: esp32c3: Fix wrong placement of Kconfig
Fixes a wrong placement of a Kconfig which was put into the
wrong file and was bleeding through to every board

Signed-off-by: Jamie McCrae <jamie.mccrae@nordicsemi.no>
2024-11-30 09:36:07 +01:00
Yong Cong Sin
e6dd68ec89 arch: riscv: introduce CONFIG_RISCV_GP_PURPOSE choice
Introduce `CONFIG_RISCV_GP_PURPOSE` choice to make sure that only
one of `CONFIG_RISCV_GP` or `CONFIG_RISCV_CURRENT_VIA_GP` can be
enabled, instead of relying of dependencies.

To do that, introduce a new
`CONFIG_RISCV_SOC_HAS_GP_RELATIVE_ADDRESSING` that can be selected
by SoC when it implemented global pointer (GP) initialization for
relative addressing in its linker.

`CONFIG_RISCV_GP` will be the default choice when
`CONFIG_RISCV_SOC_HAS_GP_RELATIVE_ADDRESSING=y`

Signed-off-by: Yong Cong Sin <ycsin@meta.com>
Signed-off-by: Yong Cong Sin <yongcong.sin@gmail.com>
2024-11-28 12:51:09 +01:00
Sylvio Alves
36d41181be soc: esp32c3: add FH4X type and SoC revision
FH4X SoC type contains improvements in ROM code that
can save up to 35kB of memory.

Update hal_espressif in order to select proper linker
file based on upon SoC model.

Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
2024-11-27 21:06:51 +00:00