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Raffael Rostagno eb606a8e7d soc: esp32: Update IRQ config for shared allocator 
Update IRQ handling related files to unify interrupt controller
between Xtensa and RISCV devices.

Signed-off-by: Raffael Rostagno <raffael.rostagno@espressif.com>
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
2025-04-02 19:02:27 +02:00
..
common soc: esp32: Update IRQ config for shared allocator 2025-04-02 19:02:27 +02:00
esp32 soc: esp32: Update IRQ config for shared allocator 2025-04-02 19:02:27 +02:00
esp32c2 soc: esp32: Update IRQ config for shared allocator 2025-04-02 19:02:27 +02:00
esp32c3 soc: esp32: Update IRQ config for shared allocator 2025-04-02 19:02:27 +02:00
esp32c6 soc: esp32: Update IRQ config for shared allocator 2025-04-02 19:02:27 +02:00
esp32s2 soc: esp32: Update IRQ config for shared allocator 2025-04-02 19:02:27 +02:00
esp32s3 soc: esp32: Update IRQ config for shared allocator 2025-04-02 19:02:27 +02:00
CMakeLists.txt
Kconfig soc: espressif: esp32c6: Add LP Core 2025-03-21 17:05:20 +01:00
Kconfig.defconfig
Kconfig.soc
Kconfig.sysbuild soc: espressif: Default MCUboot mode for ESP32 family 2024-09-16 20:17:44 +02:00
Kconfig.ulp boards: espressif: esp32c6: Add LP Core board support 2025-03-21 17:05:20 +01:00
soc.yml boards: espressif: esp32c6: Add LP Core board support 2025-03-21 17:05:20 +01:00