based on uart rom functions, also enable console driver
on top if this driver enabling logging
Signed-off-by: Felipe Neves <felipe.neves@espressif.com>
Zephyr is now able to convert ELF binary to the EFI application for
launching directly from the EFI firmware. The bootloader is not needed
and the information about grub was removed.
Signed-off-by: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
The default CONFIG_APIC_TIMER_IRQ_PRIORITY is 4, but it should be 1 for
ACRN. That's why the testcase failed due to no timer interrupt was
triggered.
And we also temporary adjust the testing IRQ for dynamic isr due to it
conflict with the IRQ of the APIC TSC deadline TIMER.
Fixes#36203.
Signed-off-by: Enjia Mai <enjiax.mai@intel.com>
for up_squared board, we already support to use UEFI bootable
method to run zephyr tests, so update the document to use
this UEFI method, rather than legacy BIOS stuff.
Signed-off-by: Chen Peng1 <peng1.chen@intel.com>
Add watchdog support to the mimxrt685 platform.
The mimxrt685 platform is excluded from the watchdog
test case because the test case uses variables in the
noinit section that need to be retained through a reset
but the rt685 does not retain this memory through a
reset.
Signed-off-by: David Leach <david.leach@nxp.com>
* Move definition of flexspi_nor_config_t into soc/ dir so it can
be shared by all i.MX RT based boards.
* Use Kconfig symbol CONFIG_NXP_IMX_RT_BOOT_HEADER instead of
HAL define (which is set based on the Kconfig symbol)
* Rename board files to flexspi_nor_config.c since they
are already namespaced by the board dir.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
This fixes an issue that surfaced with Zephyr v2.6.0,
where the GPIO driver has not completed initialization
when attempting to use it during POST_KERNEL with
KERNEL_INIT_PRIORITY_DEFAULT.
Signed-off-by: Alex Tsamakos <alex@actinius.com>
Add Atmel sam0 sercom[uart] pinctrl bindings and implements pinctrl at
driver level. It changes all sam0 boards to use new feature and remove
pinmux driver dependency for sercom[uart]. The samples that require a
binding were update to keep consistency and avoid errors.
Signed-off-by: Gerson Fernando Budke <nandojve@gmail.com>
Adds support for PWM LEDs (red, green, blue) to the mimxrt685_evk board
by adding devicetree nodes and aliases, and configuring the associated
pinmuxes. The red PWM LED is disabled by default because it's connected
to the same PWM channel as the blue PWM LED.
Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
Some devicetre overlays do not reflect the recent rename to make NS
variants of boards with TF-M support have more consistent names; fix
it.
Signed-off-by: Martí Bolívar <marti.bolivar@nordicsemi.no>
On R-Car the Cortex R7 is usually not the boot processor.
This configuration file make use of the Cortex A57 processor,
to initialize the Cortex R7.
It boils down to few steps:
- Apply power to the Cortex R7
- Set the boot address for the Cortex R7
- loading a firmware
- releasing the Cortex R7 reset
This configuration file also rely on A57 bootloaders,
to initialize device, memory, and security groups.
This file has been tested on openocd 0.10.0+dev-01508-gf79c90268-dirty,
shipped with zephyr sdk 0.12.4, and on openocd master
65c9653cc768f77a5e8cf2af73e0f40d614bdec2.
Thread awareness is possible thanks to this patch:
http://openocd.zylin.com/#/c/6369/
Signed-off-by: Julien Massot <julien.massot@iot.bzh>
Various non-secure variants of boards with SoCs that have Trusted
Firmware M support were recently renamed without any deprecations
added for the old names. This unnecessarily breaks the build for out
of tree users.
Fix that by adding the following deprecations (deprecated name ->
replacement name):
bl5340_dvk_cpuappns -> bl5340_dvk_cpuapp_ns
mps2_an521_nonsecure -> mps2_an521_ns
musca_b1_nonsecure -> musca_b1_ns
musca_s1_nonsecure -> musca_s1_ns
nrf5340dk_nrf5340_cpuappns -> nrf5340dk_nrf5340_cpuapp_ns
nrf9160dk_nrf9160ns -> nrf9160dk_nrf9160_ns
Signed-off-by: Martí Bolívar <marti.bolivar@nordicsemi.no>
Provide configurations for the nRF52840 DK and nRF5340 DK boards.
Adjust the test to cover specifics of I2S peripherals on nRF SoCs
(need of starting RX and TX simultaneously, lack of internal loopback).
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
Running postbuild.sh script after TF-M builds is a command,
to be executed after build, not a post-build byproduct.
Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
This commit adds support for SDMMC in stm32h747i_disco.
This commit is tested with fat fs list file example in
samples/subsys/fs/fatfs.
Signed-off-by: Affrin Pinhero <affrin.pinhero@hcl.com>
Create version 2 of the MEC GPIO driver to support MEC172x to not
interfere with MEC152x. When the MEC172x ECIA interrupt aggregator
driver is ready, this driver will use ECIA for registering GPIO
interrupt callbacks instead of maintaining its own interrupt table.
Add V2 DT binding.
Add the Kconfig configuration settings for the MEC172x GPIO
V2 driver at the SoC and board level.
Add port id to DT allowing use of DT FOR EACH macro in the driver.
Signed-off-by: Scott Worley <scott.worley@microchip.com>
LIS2DH12TR has an internal pull-up connected to SDA0 pin, while this pin
is connected directly to GND on PCB. This results in constant power
consumption, which can be prevented by disconnecting internal SDA0
pull-up. Do so by adding 'disconnect-sdo-sa0-pull-up' DT property, so
that accelerometer driver will send a proper command during boot.
Signed-off-by: Marcin Niestroj <m.niestroj@emb.dev>
Using GPIO_ACTIVE_HIGH explicitly says what is the active level of GPIO,
so prefer that instead of using 0.
Signed-off-by: Marcin Niestroj <m.niestroj@emb.dev>
Update Microchip XEC RTOS timer driver adding MEC172x support and
using more device tree properities in the driver. We must also update
the XEC counter driver to use the new GIRQ DT properties.
Add new properties to RTOS timer and RTC timer YAML. These two timers
are linked due to option using a high speed timer for kernel busy wait.
Add Kconfig logic for XEC RTOS timer to MEC172x SoC.
Enable the Microchip XEC RTOS timer in the MEC172x evaluation board.
Add device tree nodes for most peripeherals.
Signed-off-by: Scott Worley <scott.worley@microchip.com>
This reverts commit 445a23a167.
This change was made with the incorrect assumption that using IBECC in
an ACRN VM is a valid use case. Turns out that ACRN will always manage
the IBECC access itself and the Zephyr driver is only useful for running
natively on the hardware.
Signed-off-by: Johan Hedberg <johan.hedberg@intel.com>
Add driver implementation and header files for a MEC172x
aggregated interrupt driver. Enable the parent(ECIA) node
to have the driver initialize interrupt hardware for use.
Enable child nodes for those GIRQs used for aggregation.
Refer to chip documention for the list of GIRQs restricted
to aggregation and those which support direct mode.
Add chip level device tree node for MEC172x EC interrupt
aggregator parent and GIRQ children. Each child node contains
a list of sources representing the source bit position in the
GIRQ registers.
Add DT bindings for ECIA and GIRQ nodes.
Add build file(s) and configuration items for the MEC172x ECIA
aggregated interrupt driver. Add and enable the MEC172x interrupt
driver on the MEC172x evaluation board(EVB). Enable parent node to
initialize ECIA hardware. Child nodes are left disabled until a
future driver needs them.
Signed-off-by: Scott Worley <scott.worley@microchip.com>
This commit adds support for SDMMC driver, Which
was missing. THi commit will solveserror SDMMC init
error on stm32l496g_disco boards.
Signed-off-by: Affrin Pinhero <affrin.pinhero@hcl.com>
This commit adds support for SDMMC driver,
Which was missing. THi commit will solves
error SDMMC init error on STm32F746G_DISCO
boards.
Signed-off-by: Affrin Pinhero <affrin.pinhero@hcl.com>
Add support for sam_e70_xplained, sam_v71_xult based on TC0 counter.
Note: TC module is a 16-bit counter. Even with slow, 32768 Hz input
clock the time span counted by the driver is short.
Signed-off-by: Piotr Mienkowski <piotr.mienkowski@gmail.com>
This board has the capability to use SERCOM2 as an i2c
interface on pins 8 and 9.
This adds the neccessary pinmux settings and devicetree
node.
Tested with the i2c shell module.
Signed-off-by: Leonard Pollak <leonardp@tr-host.de>
This commit updates the supported features of stm32l5 and stm32wl boards
to match the devicetree configuration.
- add link to board defconfig and board.dts
- sort supported features table alphabethically by interface.
Additionally CRYP peripheral is added as supported feature to the
mikroe_mini_m4_for_stm32 board documentation.
Signed-off-by: Thomas Stranger <thomas.stranger@outlook.com>
SRAM partitioning for non-secure should be done via a reserved-memory
node and not fixed-partitions. fixed-partitions is meant for flash
style devices.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
The stm32l47r soc has a dma of type dma-v2, so the cells have
only 3 elements,. This adpat for the quadspi periph.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
This adds the ability to create Ethernet bridges for connecting
separate Ethernet segments together to appear as a single
Ethernet network.
This mimics the Linux functionality of the same name.
Signed-off-by: Nicolas Pitre <npitre@baylibre.com>
Implement a clock control driver for Microchip MEC172x handling
configuring the 32 KHz input sources for the PLL and peripheral-32k
clock domains. MEC172x differs from MEC152x. MEC152x had one 32K source
for both PLL and peripherals. MEC172x allows the two domains to use
independent 32 KHz sources. Device tree updated to provide addresses
of hardware used by the driver.
Signed-off-by: Scott Worley <scott.worley@microchip.com>
