The test suite is failing on qemu_cotext_a9 due to stack overflow.
Apparently this issue can also be observed on main after enabling
STACK_SENTINEL, however the test only started crashing after TCP
changes.
Signed-off-by: Robert Lubos <robert.lubos@nordicsemi.no>
Make use of the status field, reported by TCP, in the socket receive
callback. This allows to differentiate a graceful connection shutdown
from actual errors at TCP level (transmission timeout or RST received).
In case of error reported from TCP layer, set a new SOCK_ERROR flag on
the socket, and store the error code in the net_context user_data.
Signed-off-by: Robert Lubos <robert.lubos@nordicsemi.no>
Make use of the status argument in the recv_cb() callback function -
instead of blindly reporting ECONNRESET whenever TCP context is
dereferenced, indicate whether an actual error condition happened (by
setting respective errno value) or a graceful shutdown took place (by
setting status to 0).
Signed-off-by: Robert Lubos <robert.lubos@nordicsemi.no>
Add the ability to have multiple irq priority levels which are not
masked by irq_lock() by adding CONFIG_ZERO_LATENCY_LEVELS.
If CONFIG_ZERO_LATENCY_LEVELS is set to a value > 1 then multiple zero
latency irqs are reserved by the kernel (and not only one). The priority
of the zero-latency interrupt can be configured by IRQ_CONNECT.
To be backwards compatible the prio argument in IRQ_CONNECT is still
ignored and the target prio set to zero if CONFIG_ZERO_LATENCY_LEVELS
is 1 (default).
Implements #45276
Signed-off-by: Christoph Coenen <ccoenen@baumer.com>
Some sockets (UDP sockets at least) do not generate "<N>,CLOSED"
messages when the WiFi network drops. As a result the networking stack
thinks these sockets are still open after the network has dropped, and
after any subsequent reconnections.
This affects the DNS resolver library in particular, which leaves UDP
sockets open permanently by default.
Manually close these sockets when the network drops to ensure a clean
state the next time the network connects.
Signed-off-by: Jordan Yates <jordan.yates@data61.csiro.au>
`esp_close_work` can be queued from the `on_cmd_closed`, which clears
`ESP_SOCK_CONNECTED` and sets `ESP_SOCK_CLOSE_PENDING`, but does no
further work. The receive callback should still be run with no data when
the socket is closed through this mechanism.
Signed-off-by: Jordan Yates <jordan.yates@data61.csiro.au>
Previous check in the if-statement would never allow to send last
segment if msg->len + 2 == MTU * x.
Signed-off-by: Pavel Vasilyev <pavel.vasilyev@nordicsemi.no>
Use the dedicated `DT_INST_STRING_TOKEN` macro instead of manually
retrieving `DT_DRV_INST`.
Signed-off-by: Jordan Yates <jordan.yates@data61.csiro.au>
Added macro to test that a value falls within a defined range, including
the provided end points.
Signed-off-by: Jordan Yates <jordan.yates@data61.csiro.au>
Add a variety of missing `DT_INST` and `_OR` variants for working with
`STRING_TOKEN` and `STRING_UPPER_TOKEN` macros.
Signed-off-by: Jordan Yates <jordan.yates@data61.csiro.au>
Get actual keys from references when PSA crypto is enabled.
A more secure method should be implemented once 802.15.4 platforms
support other than clear text keys.
Signed-off-by: Eduardo Montoya <eduardo.montoya@nordicsemi.no>
Remove NET_TCP_BACKLOG_SIZE from KConfig and from test,
because it's not present anymore in current version of TCP stack.
Signed-off-by: Andrey Dodonov <Andrey.Dodonov@endress.com>
For a library which already provides a multi-thread aware errno, use
that instead of creating our own internal value.
Signed-off-by: Keith Packard <keithp@keithp.com>
Xilinx AXI UART Lite v2.0[1] has the following clause for both RX and TX
FIFO respectively:
When a read request is issued to an empty FIFO, a bus error (SLVERR) is
generated and the result is undefined.
When a write request is issued while the FIFO is full, a bus
error (SLVERR) is generated and the data is not written into the FIFO.
To protect this, we have:
xlnx_uartlite_read_status(dev) & STAT_REG_RX_FIFO_VALID_DATA, and
xlnx_uartlite_read_status(dev) & STAT_REG_TX_FIFO_FULL
but these are not enough for multi-threaded apps. Consider two threads
calling poll_out(), it is always possible for a thread to be swapped out
right after reading the status register, the other thread fill the TX FIFO,
and the original thread is swapped back to write more data to the FIFO
because previously read status doesn't indicate the FIFO is full.
To close this race condition, this commit uses a spinlock for each FIFO.
This ensures that only one thread accesses the FIFO even for SMP cases.
This closes#45302.
[1] https://docs.xilinx.com/v/u/en-US/pg142-axi-uartlite
Signed-off-by: Yasushi SHOJI <yashi@spacecubics.com>
Ensure callee registers included in coredump.
Push callee registers onto stack and pass as param to
z_do_kernel_oops for CONFIG_ARMV7_M_ARMV8_M_MAINLINE
when CONFIG_EXTRA_EXCEPTION_INFO enabled.
Signed-off-by: Mark Holden <mholden@fb.com>
Add partial pin control support for the imx8mp. Since the UART driver is
not currently enabled, pin control cannot be tested on this platform.
Therefore, only the DTS definitions required to set the pinmux options
are present for this platform, and are not being applied (since
CONFIG_PINCTRL=n).
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Add initial pin control support for the A53 core of the imx8mm. Since
the UART console driver is not currently enabled for this platform,
there is no way to test the full pin control enablement. Therefore,
CONFIG_PINCTRL is still not selected for this platform, although the
required DTS definitions and pin control headers are present.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Add pin control support to gpio_imx driver, so that GPIO pin muxes will
be selected when the use configures a pin as GPIO.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Add additional pin controller settings for iMX application core SOCs, as
well as a "fallback" pin control setting.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Add pin control support for IOMUXC peripheral present
on mimx8ml8_m7 soc. This reuses the existing pin
control driver for the IOMUXC peripheral, but uses a
new header and compatible binding to handle the
different register layout on this SOC.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Add pin control support for IOMUXC peripheral present
on mimx8mq6_m4 soc. This reuses the existing pin
control driver for the IOMUXC peripheral, but uses a
new header and compatible binding to handle the
different register layout on this SOC.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Add pin control support for mcimx7_m4 SOC. This reuses the existing pin
control driver for the IOMUXC peripheral, but uses a new header and
compatible binding to handle the different register layout on this SOC.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Add pin control support for mcimx6x. The IOMUXC peripheral present on
this SOC is identical to the one used on the iMX RT10xx series, so the
dts bindings are reused.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Add pin control group definitions for all iMX application cores. This
commit does not enable pin control for any iMX cores, as the SOC level
support is not present, but does define the require pin mux settings for
all boards.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Refactor iMX RT pin control support to use more generic names, as the
IOMUXC peripheral is present on non RT iMX application cores.
Additionally, make selection of the pin control driver occur at the SOC
level.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
This builtin gcc function is not available in xcc compiler.
Adding a memory compiler barrier as it is done in compiler_barrier.
compiler_barrier() and __sync_synchronize() are not the same, the
former is a sw barrier while the latter can be a hw barrier
like (mfence/sfence) in X86.
I didn't find anything equivalent for xtensa so just implementing a
SW barrier.
Signed-off-by: Flavio Ceolin <flavio.ceolin@intel.com>
This add a new sample application to test and validate
the stm32 octospi driver on the NOR octo-flash present on
stm32 disco kits
There should be a special case to erase the complete flash.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
This commit enables the octo SPI peripheral to the flash-nor
on the target board b_u585i_iot02a from STMicroelectronics.
Note that JESD16 requires 9 dwords for the sdfp table.
The configuration is for OctoSPI bus through IO manager.
The NOR octoflash is MX25LM51245 or compatible.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
This commit enables the octo SPI peripheral to the flash-nor
on the target board stm32l562e_dk from STMicroelectronics.
Note that JESD16 requires 9 dwords for the sdfp table.
The NOR octoflash is MX25LM51245 or compatible.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
Simplifies the driver and Gives a generic function to prepare the Regular
commands for each instruction.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
This is the stm32 octospi driver based on the exisitng quadspi
for stm32 devices and source code from the STM32Cube.
This drivers initialized the peripheral and the NOR memory
in SPI or OctoSPI mode with STR or DTR data Transfer rates.
The NOR-flash can provide the SDFP table directly (if supported)
or through the DeviceTree.
Limitation: no DMA transfer.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
