Pull request https://github.com/zephyrproject-rtos/zephyr/pull/24873
marked all the struct devices const.
However, the linker scripts were never updated to actually allocate
the struct devices in ROM. They're still in RAM, so the main benefit
of this work has not been realized.
Fix it.
Signed-off-by: Martí Bolívar <marti.bolivar@nordicsemi.no>
The `.eh_frame_hdr` and `.eh_frame` ROM sections, which contain read-
only C++ exception handling information, are currently specified in
`cplusplus-ram.ld`, and this can cause the linker output location
counter to take a ROM region address while in the RAM region.
This commit relocates these sections to `cplusplus-rom.ld` in order to
prevent the linker output location counter from getting corrupted.
For more details, refer to the issue #35972.
Signed-off-by: Stephanos Ioannidis <root@stephanos.io>
When a device is defined a new pointer to a device will be created in
the "z_pm_device_slots" region, effectively creating a device array with
the same size as the number of system devices. This array is then used
by the device PM subsystem to keep track of suspended devices during
power transitions.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
The `CONFIG_LINKER_SORT_BY_ALIGNMENT` config, which is enabled by
default, causes the sections containing C++ exception handling
information to be re-ordered for certain targets (in particular, the
64-bit arch targets). This effectively breaks the required "crtbegin.o
-> others -> crtend.o" order and causes the address of the
__EH_FRAME_BEGIN__ symbol to be invalid; thereby, causing C++
exception unwinding to fail.
This commit adds SORT_NONE property to these sections in order to
ensure that the linking order specified in the linker command line is
maintained.
Signed-off-by: Stephanos Ioannidis <root@stephanos.io>
Fixes part of: #32448
This commit updates the CMake CMAKE_CXX_LINK_EXECUTABLE to include
crtbegin.o and crtend.o at the right locations when linking with gcc.
It also updates linker scripts to ensure proper location of the
exception header frame sections.
This ensure proper handling of exceptions for those architectures
- x86
- xtensa
- riscv32
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Signed-off-by: Torsten Rasmussen <Torsten.Rasmussen@nordicsemi.no>
syntax ". += length;" not work with arcmwdt toolchain, let's using
". = . + length;", which both work with gnu and arcmwdt toolchain.
Signed-off-by: Watson Zeng <zhiwei@synopsys.com>
This allows interrupt service routine to be declared with
the __isr tag so they can be placed in the correct linker
section. The first would be putting them into the pinned
section.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
This adds the necessary bits for linker scripts and source code
to specify which symbols need to be pinned in memory. This is
needed for demand paging as some functions and data must reside
in memory all the time and cannot be paged out (e.g. paging,
scheduler, and interrupt routines for functionality).
This is up to the arch/SoC/board to define the sections in
their linker scripts as the pinned section may need special
alignment which cannot be done in common script snippets.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
This adds the necessary bits for linker scripts and source code
to specify which symbols are needed for boot process so they
can be grouped together.
One use of this is to group boot related code and data so these
won't interval with other kernel and application for better
caching.
This is a must for demand paging as some functions and data
must be available during the boot process and before the memory
manager is initialized. During this time, paging cannot be used
so symbols linked in virtual memory space are unavailable.
This is up to the arch/SoC/board to define the sections in
their linker scripts as section may need special alignment
which cannot be done in common script snippets.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
There is exactly one function being defined with TEXT_START
macro so the x86-32 __start can appear at the beginning of
text section. Since no one else is using it, better remove
TEXT_START to simplify things.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
Do basic preparations for building code for ARCv3 HS6x
* add ISA_ARCV3 and CPU_HS6X config options
* add off_t type support for __ARC64__
* use elf64-littlearc format for linking
* use arc64 mcpu for CPU_HS6X
Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
Signed-off-by: Evgeniy Paltsev <PaltsevEvgeniy@gmail.com>
Due to the use of gperf to generate hash table for kobjects,
the addresses of these kobjects cannot change during the last
few phases of linking (especially between zephyr_prebuilt.elf
and zephyr.elf). Because of this, the gperf generated data
needs to be placed at the end of memory to avoid pushing symbols
around in memory. This prevents moving these generated blocks
to earlier sections, for example, pinned data section needed
for demand paging. So create placeholders for use in
intermediate linking to reserve space for these generated blocks.
Due to uncertainty on the size of these blocks, more space is
being reserved which could result in wasted space. Though, this
retains the use of hash table for faster lookup.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
In case of ARC MWDT toolchain and C++ support enabled the Zephyr .init*
section conflicts with .init* sections derived from toolchain libs.
Let's add 'z_' prefix to Zephyr .init* section (and therefore .device
section as they share the same macros) to make Zephyr section name
unique.
Signed-off-by: Evgeniy Paltsev <PaltsevEvgeniy@gmail.com>
This NETWORK_RAM_SECTIONS() macro can now be overridden (in board
specific linker.ld file) when one needs to force explicit placement
of network interface' related elements.
Signed-off-by: Lukasz Majewski <lukma@denx.de>
The assert error message when CONFIG_KOBJECT_TEXT_AREA is
too small is confusing. Probably the original idea is for
the linker to substitue CONFIG_KOBJECT_TEXT_AREA with
the actual value. However, linker does not do that.
So change the message to say that the kconfig value needs
to be increased.
Fixes#34387
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
Added implementation of log_msg2 which is creating log messages
using cbprintf packaging and storing them in circular ring buffer
(mpsg_pbuf).
Signed-off-by: Krzysztof Chruscinski <krzysztof.chruscinski@nordicsemi.no>
Adds a public macro for creating memory regions from devicetree nodes.
`DT_REGION_FROM_NODE_STATUS_OKAY` declares the memory regions for
consumption by ld, assuming the node exists and has `status = "okay"`.
Signed-off-by: Jordan Yates <jordan.yates@data61.csiro.au>
Split ARM and ARM64 architectures.
Details:
- CONFIG_ARM64 is decoupled from CONFIG_ARM (not a subset anymore)
- Arch and include AArch64 files are in a dedicated directory
(arch/arm64 and include/arch/arm64)
- AArch64 boards and SoC are moved to soc/arm64 and boards/arm64
- AArch64-specific DTS files are moved to dts/arm64
- The A72 support for the bcm_vk/viper board is moved in the
boards/bcm_vk/viper directory
Signed-off-by: Carlo Caione <ccaione@baylibre.com>
Commit 0a7b65e tweaked the CREATE_OBJ_LEVEL macro in such a way
that it would break the expected sorting order.
For example if you had 2, 19, 20, 30 as the level, we'd end up sort
these to be 19, 2, 20, 30.
Fix this by adding aditional "_" symbol after the init level counter.
That allows to keep correct sort order (for both GNU and MWDT
toolchains) and distinguish init level counter from section suffix
(for MWDT toolchain).
Fixes zephyrproject-rtos#33464
Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
MWDT toolchain adds additional suffix to sections name
in case of ffunction-sections / fdata-sections are enabled.
Let's pick a single set of rules and syntax that work.
Signed-off-by: Watson Zeng <zhiwei@synopsys.com>
New macro GROUP_ROM_LINK_IN for text/rodata sections
New macro GROUP_NOLOAD_LINK_IN for bss/noinit sections
GROUP_FOLLOWS_AT is unused anywhere in the kernel for
years now and has been removed.
Signed-off-by: Watson Zeng <zhiwei@synopsys.com>
Since linker_final_pass.cmd is the actual linker script being
used to link the final Zephyr binary, rename it to linker.cmd.
This also renames LINKER_PASS2 to LINKER_ZEPHYR_FINAL simply
to clarify what it is used for, instead of ambiguous pass #n.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
Using this actually would result in a linker input section being
put between output sections which is not correct syntax.
We have never seen this simply because the generated ones would
be included instead of the in-tree ones. So remove this just in
case, instead of linker errors.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
There's no need to duplicate the linker section for each architecture.
Instead, move the section declaration to common-rom.ld.
Signed-off-by: Carles Cufi <carles.cufi@nordicsemi.no>
Adds a Proxy callback structure with a callback for Node ID enable and
disable. This API follows the Friend and LPN API pattern in mesh/main.h,
and can be expanded with more callbacks later.
Signed-off-by: Trond Einar Snekvik <Trond.Einar.Snekvik@nordicsemi.no>
We need to do a few things differently if we are to support
a virtual memory map, i.e. CONFIG_MMU where CONFIG_KERNEL_VM_BASE
is not the same as CONFIG_SRAM_BASE_ADDRESS.
- All sections must be specified with a VMA and LMA, where
VMA is the virtual address and LMA is the physical memory
location.
- All sections must be specified with ALIGN_WITH_INPUT to
keep VMAs and LMAs synchronized
To do this, the existing linker macros need some adjustment:
- GROUP_LINK_IN undefined when CONFIG_KERNEL_VM_BASE is not
the same as CONFIG_SRAM_BASE_ADDRESS.
- New macro GROUP_ROM_LINK_IN for text/rodata sections
- New macro GROUP_NOLOAD_LINK_IN for bss/noinit sections
- Implicit ALIGN_WITH_INPUT for all sections
GROUP_FOLLOWS_AT is unused anywhere in the kernel for years
now and has been removed.
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
__tbss_start should be a virtual address.
__tdata_start should also be a virtual address, unless we're
using XIP in which case each thread should copy its thread-
local data out of flash.
Fixes issues with a kernel linked at a virtual address.
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
Following the idiom used for system calls, add script support to read
the initial application binary to identify which devices are defined,
and to use their offset in the device array as their unique handle
rather than the externally-defined ordinal from devicetree. The
device dependency arrays are updated to use these handles.
Signed-off-by: Peter Bigot <peter.bigot@nordicsemi.no>
Move the busy status from a global atomic bit sequence to atomic flags
in the device PM state. While this temporarily adds 4 bytes to each
PM structure the whole device PM infrastructure will be refactored and
it's likely the extra memory can be recovered.
Signed-off-by: Peter Bigot <peter.bigot@nordicsemi.no>
Separate the state indicator of whether the initialization function
has been invoked from the success or failure of the initialization.
This allows precise confirmation that the device is ready (i.e. it has
been initialized, and that initialization succeeded).
Signed-off-by: Peter Bigot <peter.bigot@nordicsemi.no>
Add support for backup SRAM initialization found in multiple STM32
microcontrollers. Linker script facilities are also provided to make it
easy to define variables in the backup SRAM.
Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
In binutils SORT is an alias for SORT_BY_NAME. Don't confuse people
by replacing explicit use of the actual directive with an alias for
that same directive.
Signed-off-by: Peter Bigot <peter.bigot@nordicsemi.no>
The CONFIG_KERNEL_COHERENCE framework merged with a typo that left its
validation asserts disabled. But it was written before the "kernel
stacks" feature merged, and so missed the K_KERNEL_STACK_* macros,
which need to put their stacks into __stackmem and not merely
__noinit.
Turning the asserts on exposed the bug.
Fixes#32112
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
This lets the linker tell us what kind of alignment is required
for both tdata and tbss data when copying them into stack.
If they are not aligned as expected by the toolchain, generated
code would be accessing incorrect location for thread variables.
Fixes#32015
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
The linker script defines `z_mapped_size` as follows:
```
z_mapped_size = z_mapped_end - z_mapped_start;
```
This is done with the belief that precomputed values at link time will
make the code smaller and faster.
On Aarch64, symbol values are relocated and loaded relative to the PC
as those are normally meant to be memory addresses.
Now if you have e.g. `CONFIG_SRAM_BASE_ADDRESS=0x2000000000` then
`z_mapped_size` might still have a reasonable value, say 0x59334.
But, when interpreted as an address, that's very very far from the PC
whose value is in the neighborhood of 0x2000000000. That overflows the
4GB relocation range:
```
kernel/libkernel.a(mmu.c.obj): in function `z_mem_manage_init':
kernel/mmu.c:527:(.text.z_mem_manage_init+0x1c):
relocation truncated to fit: R_AARCH64_ADR_PREL_PG_HI21
```
The solution is to define `Z_KERNEL_VIRT_SIZE` in terms of
`z_mapped_end - z_mapped_start` at the source code level. Given this
is used within loops that already start with `z_mapped_start` anyway,
the compiler is smart enough to combine the two occurrences and
dispense with a size counter, making the code effectively
slightly better for all while avoiding the Aarch64 relocation
overflow:
```
text data bss dec hex filename
1216 8 294936 296160 484e0 mmu.c.obj.arm64.before
1212 8 294936 296156 484dc mmu.c.obj.arm64.after
1110 8 9244 10362 287a mmu.c.obj.x86-64.before
1106 8 9244 10358 2876 mmu.c.obj.x86-64.after
```
Signed-off-by: Nicolas Pitre <npitre@baylibre.com>
XCC Clang doesn't emit load address when a section
is empty, resulting in __tdata_start not being
defined. So put a #ifdef guard for the thread local
storage linker script to avoid this issue.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
Both _IRQ_VECTOR_TABLE_SECTION_NAME and _SW_ISR_TABLE_SECTION_NAME
are defined with asterisk at the end in an attempt to include
all related symbols in the linker script. However, these two
macros are also being used in the source code to specify
the destination sections for variables. Asterisks in the name
results in older GCC (4.x) complaining about those asterisks.
So create new macros for use in linker script, and keep
the names asterisk free.
Fixes#29936
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
Page tables created at build time may not include the
gperf data at the very end of RAM. Ensure this is mapped
properly at runtime to work around this.
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
These are needed on MMU systems and define where the kernel
image resides in virtual memory at boot so that it may be
memory-mapped.
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
MWDT toolchain adds additional suffix to sections name in case of
ffunction-sections / fdata-sections are enabled.
The 40d3653758 commit
(device: add post-process of elf file to manage device handles)
breaks linkage with MWDT toolchain as it adds new sections
which are not meet MWDT requirements.
Let's pick a single set of rules and syntax that work for all
toolchain.
Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
Page tables created at build time may not include the
gperf data at the very end of RAM. Ensure this is mapped
properly at runtime to work around this.
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
These are needed on MMU systems and define where the kernel
image resides in virtual memory at boot so that it may be
memory-mapped.
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
Following the idiom used for system calls, add script support to read
the initial application binary to identify which devices are defined,
and to use their offset in the device array as their unique handle
rather than the externally-defined ordinal from devicetree. The
device dependency arrays are updated to use these handles.
Signed-off-by: Peter Bigot <peter.bigot@nordicsemi.no>
This adds a somewhat special purpose IPC mechanism. It's intended for
applications which have a "work queue" like architecture of discrete
callback items, but which need the ability to schedule those items
independently in separate threads across multiple CPUs. So P4 Work
items:
1. Can run at any Zephyr scheduler priority and with any deadline
(this feature assumes EDF scheduling is enabled)
2. Can be submitted at any time and from any context, including being
resubmitted from within their own handler.
3. Will preempt any lower priority work as soon as they are runnable,
according to the standard rules of Zephyr priority scheduling.
4. Run from a pool of worker threads that can be allocated efficiently
(i.e. you need as many as the number of CPUs plus the number of
preempted in-progress items, but no more).
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
