Commit graph

9 commits

Author SHA1 Message Date
Daniel Leung
8ce758a8ff linker: warn about orphan sections
This adds a linker flag and necessary changes to linker scripts
so that linker will warn about orphan sections.

Relates to #5534.

Signed-off-by: Daniel Leung <daniel.leung@intel.com>
2018-10-09 08:23:41 -04:00
Daniel Leung
2fed930f4e linker: allow SoC to insert linker script fragments
This allows the SoC to specify some additional linker script
fragments into the bss, data and read-only data sections.

For example, the Cypress PSOC6 has a few input sections that
must be put into bss and data sections. Without specifying
these in the linker script, they are consider orphan sections
and the placement is based on linker heuristic which is
arbitrary.

POSIX is not supported as the main linker script is
provided by the host system's binutils and we have no control
over it. Also, currently Xtensa SoCs have their own linker
scripts so there is no need to this feature.

Signed-off-by: Daniel Leung <daniel.leung@intel.com>
2018-10-09 08:23:41 -04:00
Sebastian Bøe
347f9a0a2d cmake: LD: Specify the entry point in the linker scripts
The entry point can and therefore should be set by linker
scripts. Whenever possible one should express things in the source
language, be it .c or .ld, and not in code generators or in the build
system.

This patch removes the flag -eCONFIG_KERNEL_ENTRY from the linker's
command line and replaces it with the linker script command

ENTRY(CONFIG_KERNEL_ENTRY)

Signed-off-by: Sebastian Bøe <sebastian.boe@nordicsemi.no>
2018-07-03 17:18:14 -04:00
Andrew Boie
f9636d6f7e riscv32: pulpino: add some missing linker symbols
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2017-07-18 14:22:26 -07:00
Anas Nashif
397d29db42 linker: move all linker headers to include/linker
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2017-06-18 09:24:04 -05:00
Andrew Boie
bd69c3bdf0 riscv32: enable gen_isr_tables mechanism
Change-Id: Ia09d9a4d3412424dcbb25db829059a0714d81214
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2017-02-15 04:49:17 +00:00
Leandro Pereira
570634a259 kernel: Add OpenOCD support
In order for OpenOCD to have a high-level view of an RTOS, it uses the
GDB protocol to obtain symbols from the system.

The GDB protocol, however, does not allow obtaining fields from
structures directly, and hardcoding offsets is not only brittle (due to
possibly different architectures or changes in the code), it's also
infeasible considering Zephyr is highly-configurable and parts of key
structs can be compiled in or out.

Export an array with offsets for these key structs. Also add a version
element in that array to allow changes in those structs.

Change-Id: I83bcfa0a7bd57d85582e5ec6efe70e1cceb1fc51
Signed-off-by: Leandro Pereira <leandro.pereira@intel.com>
2017-02-11 03:57:19 +00:00
David B. Kinder
ac74d8b652 license: Replace Apache boilerplate with SPDX tag
Replace the existing Apache 2.0 boilerplate header with an SPDX tag
throughout the zephyr code tree. This patch was generated via a
script run over the master branch.

Also updated doc/porting/application.rst that had a dependency on
line numbers in a literal include.

Manually updated subsys/logging/sys_log.c that had a malformed
header in the original file.  Also cleanup several cases that already
had a SPDX tag and we either got a duplicate or missed updating.

Jira: ZEP-1457

Change-Id: I6131a1d4ee0e58f5b938300c2d2fc77d2e69572c
Signed-off-by: David B. Kinder <david.b.kinder@intel.com>
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2017-01-19 03:50:58 +00:00
Jean-Paul Etienne
2a8cfca4cf riscv32: added support for the pulpino soc
pulpino soc has custom-extended riscv ISA that is accounted
for if CONFIG_RISCV_GENERIC_TOOLCHAIN is not set.
(ex: bit manipulation asm opcodes)

Change-Id: I4dafc4ebc2fedcc4eb6a3dedd0412816afea6004
Signed-off-by: Jean-Paul Etienne <fractalclone@gmail.com>
2017-01-13 19:55:05 +00:00