Commit graph

51573 commits

Author SHA1 Message Date
Hou Zhiqiang
50d263d138 arm64: Do not try to bring up the cores disabled in DT node
The macro DT_FOREACH_CHILD will iterates all child nodes ignoring the
status property, this patch changes to use DT_FOREACH_CHILD_STATUS_OKAY
to avoid trying to bring up disabled cores, which only iterates the
enabled child nodes.

Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
2021-04-27 13:32:55 -04:00
Hou Zhiqiang
0700a24276 devicetree: Add DT_FOREACH_CHILD_STATUS_OKAY macro
The macro only iterates the enabled child nodes and invokes
provided macro for each node.

Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
2021-04-27 13:32:55 -04:00
Hou Zhiqiang
9681034875 arm64: Fix MPID load instruction for secondary cores
Change to load MPID for secondary cores adding offset macro
BOOT_PARAM_MPID_OFFSET.

Currently the code load MPID for secondary cores from offset 0x0
of the struct arm64_cpu_boot_params, it's working as currently
the macro BOOT_PARAM_MPID_OFFSET has value 0x0, but when the
location of the member "mpid" is changed, it can result in SMP
booting failure and the build assert won't throw out any warning.

Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
2021-04-27 13:32:18 -04:00
Daniel Leung
1117169980 kernel: generate placeholders for kobj tables before final build
Due to the use of gperf to generate hash table for kobjects,
the addresses of these kobjects cannot change during the last
few phases of linking (especially between zephyr_prebuilt.elf
and zephyr.elf). Because of this, the gperf generated data
needs to be placed at the end of memory to avoid pushing symbols
around in memory. This prevents moving these generated blocks
to earlier sections, for example, pinned data section needed
for demand paging. So create placeholders for use in
intermediate linking to reserve space for these generated blocks.
Due to uncertainty on the size of these blocks, more space is
being reserved which could result in wasted space. Though, this
retains the use of hash table for faster lookup.

Signed-off-by: Daniel Leung <daniel.leung@intel.com>
2021-04-27 13:32:00 -04:00
Daniel Leung
317dcd908f scripts: gen_kobject_list: no need to specify linker section
There is no need to specify linker section for variables in
the output. The compiled object file from the produced
source file will be further processed to have them renamed
anyway.

Signed-off-by: Daniel Leung <daniel.leung@intel.com>
2021-04-27 13:32:00 -04:00
Daniel Leung
c3711b3446 kernel: change metadata for priv_stacks to const
The metadata array for priv_stacks doesn't change and
can be marked const so this can put in ROM.

Signed-off-by: Daniel Leung <daniel.leung@intel.com>
2021-04-27 13:32:00 -04:00
Qi Feng
2e104eabfc boards: fvp_baser_aemv8r: doc: debug with Arm DS
Add document about debugging with Arm Development Studio and some
description. Standardize the names.

Signed-off-by: Qi Feng <qi.feng@arm.com>
2021-04-27 13:31:42 -04:00
Qi Feng
83530473d0 boards: arm64: doc: only list index files
So that rst files located in a certain board are not listed in board
level table of contents.

Signed-off-by: Qi Feng <qi.feng@arm.com>
2021-04-27 13:31:42 -04:00
Torsten Rasmussen
5db987f922 cmake: use WEST_PYTHON as a preferred python installation if defined.
Fixes: #34368

Now added WEST_PYTHON to list of preferred pythons to check.
WEST_PYTHON is added after PYTHON_PREFER so that a user may still
request a specific python is used by supplying
`-DPYTHON_PREFER=<python>` even when building using `west build`.

Signed-off-by: Torsten Rasmussen <Torsten.Rasmussen@nordicsemi.no>
2021-04-27 13:31:23 -04:00
Emil Gydesen
676a91636b Bluetooth: Audio: VOCS add error checks on read
The error check was removed earlier as it was assumed that
we would either get an error, or the data would be valid.
However, without an error check, we are not guarded
against bad reads.

Signed-off-by: Emil Gydesen <emil.gydesen@nordicsemi.no>
2021-04-27 13:31:06 -04:00
Emil Gydesen
449ceca2fe Bluetooth: Audio: Remove VOCS desc data check as it can be empty
If the output description of the server is empty (legal by the
spec), then we should not return an error to the application
when read. Also added some debug statements when the value is
truncated.

Signed-off-by: Emil Gydesen <emil.gydesen@nordicsemi.no>
2021-04-27 13:31:06 -04:00
Emil Gydesen
d005a62451 Bluetooth: Audio: Fix issues with setting VOCS offset state
Fixes 2 issues:
1) The write callback always returned an error
2) The auto-read of the offset state did not, unlike what the
comment suggested, retry only once and fail on the second attempt,
but rather keep retrying.

Signed-off-by: Emil Gydesen <emil.gydesen@nordicsemi.no>
2021-04-27 13:31:06 -04:00
Emil Gydesen
abb97f57dd Bluetooth: GATT: Extend GATT notify/indicate security check with auth
Add authentication check to the security checks for
GATT notify and indicate.

Signed-off-by: Emil Gydesen <emil.gydesen@nordicsemi.no>
2021-04-27 13:30:44 -04:00
Emil Gydesen
2f4ee7dcb6 Bluetooth: GATT: Verify security when notifiying or indicating
Adds a security checks when notifying or indicating, such
that we don't send notifications for characteristics that
require encryption on an unencrypted link.

Signed-off-by: Emil Gydesen <emil.gydesen@nordicsemi.no>
2021-04-27 13:30:44 -04:00
Enjia Mai
d3747db66f tests: kernel: fix two test cases of condvar hang up in SMP
Make some change on two codvar test cases to fit testing under SMP,
and shorter the test cases execution time.

Fixes #33558.

Signed-off-by: Enjia Mai <enjiax.mai@intel.com>
2021-04-27 13:30:24 -04:00
Enjia Mai
2e1ac6b46b tests: smp: cancel CONFIG_MP_NUM_CPUS limit of some testcases
Try to remove CONFIG_MP_NUM_CPUS=1 configuration for the test of
condvar, sysmutex and semaphore, in order to test SMP condition more.

Signed-off-by: Enjia Mai <enjiax.mai@intel.com>
2021-04-27 13:30:24 -04:00
Carlo Caione
5b3d499755 board: fvp_baser_aemv8r: Fix board yaml file
To make it consistent with the yaml of the other FVP board.

Signed-off-by: Carlo Caione <ccaione@baylibre.com>
2021-04-27 13:30:07 -04:00
Carlo Caione
0427d93f4a board: arm64: Add FVP Base RevC 2xAEMv8A board
Add support for the FVP Base RevC 2xAEMv8A board to be emulated using
the same FVP. For now the virtual platform is only exposing one core and
the basic set of peripherals (GICv3, ARM arch timer, PL011, etc...).

INFO    - Total complete:  256/ 256  100%  skipped:  933, failed:    0

Signed-off-by: Carlo Caione <ccaione@baylibre.com>
2021-04-27 13:30:07 -04:00
Navin Sankar Velliangiri
62149516c4 mgmt: hawkbit: Conversion of k_work API
Implement new workqueue API changes.

Signed-off-by: Navin Sankar Velliangiri <navin@linumiz.com>
2021-04-27 13:29:39 -04:00
William MARTIN
e61b957a0f drivers/i2s: stm32: Fix pinmux
Update the I2S_INIT macro to correct the i2s_pins loading.

Signed-off-by: William MARTIN <william.martin@power-lan.com>
2021-04-27 13:29:26 -04:00
Peter Bigot
d8cf822d66 doc: kernel: workqueue: add section on best practices
Refactor best practices from the API refactoring issue and integrate
them into the existing documentation.

Signed-off-by: Peter Bigot <peter.bigot@nordicsemi.no>
2021-04-27 13:29:08 -04:00
Peter Bigot
add4c1d8ef doc: kernel: workqueue: miscellaneous cleanup
Minor terminology misuse, style changes, or clarifications.

Signed-off-by: Peter Bigot <peter.bigot@nordicsemi.no>
2021-04-27 13:29:08 -04:00
Peter Bigot
0ef268f025 doc: kernel: workqueue: improve documentation on context retrieval
Reference the helper macro used to obtain the containing context
structure from a work item pointer within a work handler.  Also
document the proper way to do this for delayable work items.

Signed-off-by: Peter Bigot <peter.bigot@nordicsemi.no>
2021-04-27 13:29:08 -04:00
Peter Bigot
1f0082249e doc: kernel: workqueue: explicitly mention K_WORK_DEFINE
Point out that this macro can be used to avoid the need to initialize
a work item.  This is still of limited use since it can't statically
initialize a work item within another structure.

Signed-off-by: Peter Bigot <peter.bigot@nordicsemi.no>
2021-04-27 13:29:08 -04:00
Peter Bigot
537f966997 doc: kernel: workqueue: correct terminology misuse
Use queued uniformly when referring to items that are in a work queue,
rather than "pending" which includes items that are scheduled or
running.

Signed-off-by: Peter Bigot <peter.bigot@nordicsemi.no>
2021-04-27 13:29:08 -04:00
Peter Bigot
707dc22fb0 kernel: fix error in synchronous work cancellation return value
The return value is documented to be true if the work was pending, but
the implementation returned true only if the work was actually running
(i.e. the caller had to wait).  It should also return true if
scheduled or submitted work was cancelled.

Note that this means the return value cannot be used to determine
whether the call slept.

Signed-off-by: Peter Bigot <peter.bigot@nordicsemi.no>
2021-04-27 13:28:45 -04:00
Alberto Escolar Piedras
bcd43ff494 posix: Add missing include
The NATIVE_TASK macro uses macros from the toolchain header.
Instead of relaying on the header to be included by somebody else,
include it explicity here.

Signed-off-by: Alberto Escolar Piedras <alpi@oticon.com>
2021-04-27 13:17:36 -04:00
Robert Lubos
afaf52af66 net: trickle: Do not initialize a work item from its handler
Initializing a work item from its handler will destroy the content of
the kernel structures used to process the work item. This can lead to a
system crash for example when the delayed work is being rescheduled when
the previous run is already queued for processing but not yet executed.

Fix this by initializing the work item once during trickle timer
creation and moving the logic, previously achieved by switching the work
handler, into the new work handler.

Signed-off-by: Robert Lubos <robert.lubos@nordicsemi.no>
2021-04-27 19:48:16 +03:00
Anas Nashif
80116f1413 tests: benchmarks: footprints: this is not a test
Do not configure this as a test, this will change footprint drastically
and will skew results and tracking.

Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2021-04-27 12:15:14 -04:00
Gerson Fernando Budke
260c679af5 boards: arm: cy8ckit_062_ble: Add board rev
Introduce revision for cy8ckit_062_ble board.  Revision 0.0.0 represent
the original board schematic which connects Arduino header signals to
PSoC-6 KitProg.  The revision 1.0.0 should be used after board rework
to access other serial ports and full Arduino headers.

Signed-off-by: Gerson Fernando Budke <gerson.budke@atl-electronics.com>
2021-04-27 09:27:45 -05:00
Gerson Fernando Budke
2efa4db9e8 boards: arm: cy8ckit_062_wifi_bt: Add serial pinctrl and int
Add pinctrl and interrupt information for both cores.  The uart-6 is
the default serial communication on the kit connected to m0 core.  It
uses SCB[6] and the NVIC line 21 as interrupt source on Cortex-M0+ cpu.
The line 21 is an arbitrary value and users can select any value.  The
SCB[6] shares pins with Arduino headers D8/D9.  It may be necessary an
USB serial converter to sample signals and enable Zephyr console on PC.
The uart-5 is the default serial communication port for m4.  It is
connected to Arduino serial line.  A HW rework may need to allow
Arduino header to be useful.

Signed-off-by: Gerson Fernando Budke <gerson.budke@atl-electronics.com>
2021-04-27 09:27:45 -05:00
Gerson Fernando Budke
a24350a1a4 boards: arm: cy8ckit_062_ble: Add serial pinctrl and int
Add pinctrl and interrupt information for both m0/4 cores.  The uart-5
is the default serial communication on the kit and it is connected to
Cortex-M0+ cpu.  It uses SCB[5] and the NVIC line 21 as interrupt
source on Cortex-M0+ cpu.  The line 21 is an arbitrary value and users
can select any value.  The SCB[5] shares pins with Arduino headers
D0/D1 and it is wired with the on-board USB Serial converter.  This
means, if use wants use an external shield it must rework the board.
The uart-6 is the default serial communication for Cortex-M4 cpu, which
uses SCB[6].

Signed-off-by: Gerson Fernando Budke <gerson.budke@atl-electronics.com>
2021-04-27 09:27:45 -05:00
Gerson Fernando Budke
2bd130112a drivers: serial: psoc6: Add interrupts support
Current Cypress PSoC-6 serial driver only works using polling mode.
Add serial driver interrupt routines to allow use of interrupts.

Signed-off-by: Gerson Fernando Budke <gerson.budke@atl-electronics.com>
2021-04-27 09:27:45 -05:00
Gerson Fernando Budke
e6cba8d9c8 drivers: serial: psoc6: Rework to support pinctrl
The current serial driver uses hard code configuration.  Rework driver
to use pinctrl and enable full configuration from device tree.

Signed-off-by: Gerson Fernando Budke <gerson.budke@atl-electronics.com>
2021-04-27 09:27:45 -05:00
Marek Pieta
66b6f07ea3 tests: drivers: Add LED GPIO driver to build_all
Change adds LED GPIO driver to build_all test.

Signed-off-by: Marek Pieta <Marek.Pieta@nordicsemi.no>
2021-04-27 16:21:48 +02:00
Marek Pieta
a712c3622d drivers: led: Add LED GPIO driver
Change introduces LED GPIO driver.

Signed-off-by: Marek Pieta <Marek.Pieta@nordicsemi.no>
2021-04-27 16:21:48 +02:00
Krzysztof Chruscinski
2115964929 logging: Fix casting related C++ warnings
Fixed C++ warnings coming from implicit casting.

Signed-off-by: Krzysztof Chruscinski <krzysztof.chruscinski@nordicsemi.no>
2021-04-27 08:48:03 -05:00
Krzysztof Chruscinski
d863b93516 lib: os: cbprintf: Prevent using _Generic in C++
Add guard to not use C11 specific feature when in C++.

Signed-off-by: Krzysztof Chruscinski <krzysztof.chruscinski@nordicsemi.no>
2021-04-27 08:48:03 -05:00
Krzysztof Chruscinski
1f3758ff9e logging: Macro cleanup to fix cpp warnings
Cleanup to fix warnings coming from c++ compilation.

Signed-off-by: Krzysztof Chruscinski <krzysztof.chruscinski@nordicsemi.no>
2021-04-27 08:48:03 -05:00
Henrik Brix Andersen
d6318075b7 boards: arm: twr_ke18f: Add pinctrl dts properties
Add pinctrl-0 properties for configuration of UART, I2C, SPI, FTM,
DAC, ADC, ACMP, and PWT peripherals. These settings are based on what
is defined in the board/pinmux.c file.

Signed-off-by: Henrik Brix Andersen <hebad@vestas.com>
2021-04-27 08:43:23 -05:00
Peter Bigot
c26cdb7409 drivers: flash: spi-nor: add support for 4-byte addressing
Add a function that uses the JESD216 SFDP BFP DW16 Enter 4-Byte
Addressing parameter to put the device into 4-byte addressing mode if
one of the entry modes that's supported by the driver is available on
the device.

Perform the transition if SFDP data is provided (either by devicetree
or at runtime), or if a special devicetree property provides the entry
mode descriptor.

Signed-off-by: Peter Bigot <peter.bigot@nordicsemi.no>
2021-04-27 14:21:15 +02:00
Peter Bigot
6c4312605c drivers: flash: jesd216: improve support for address size selection
Add a helper function to decode the address byte support data from the
SFDP BFP.

Signed-off-by: Peter Bigot <peter.bigot@nordicsemi.no>
2021-04-27 14:21:15 +02:00
Peter Bigot
e0f514f670 drivers: flash: spi_nor: support 32-bit addresses in access method
Support both 24-bit and 32-bit address values when constructing the
device command.  Note that some commands require 24-bit address
regardless of mode, and some require 32-bit addresses regardless of
mode, so provide command-specific overrides of a generic (but not yet
configurable) default address size.

With this we no longer need a special interface for READ_SFDP which
uses a 24-bit address but with a wait state introduced by clocking out
a fifth command byte.

Signed-off-by: Peter Bigot <peter.bigot@nordicsemi.no>
2021-04-27 14:21:15 +02:00
Peter Bigot
cde962e789 drivers: flash: spi_nor: refactor to allow more access options
This driver abstracts most access through a generic function that
supports both read and write with and without address components in
the command.  Rework this so that instead of distinct arguments
specifying the combination of features there's a flag set that will
allow more combinations to be specified.

Signed-off-by: Peter Bigot <peter.bigot@nordicsemi.no>
2021-04-27 14:21:15 +02:00
Mario Jaun
c276088567 drivers: ethernet: stm32: SRAM3 / MPU configuration
Fixes #29915.

Implements the memory layout and MPU configuration for Ethernet buffers
for STM32H7 controllers as recommended by ST. 16 KB of SRAM3 are
are reserved for this. The first 256 B are for the RX/TX descriptors and
configured as strongly ordered, shareable memory. The rest is for RX/TX
buffers and configured as non cacheable memory. This configuration is
automatically applied for H7 chips if the SRAM3 memory is enabled in the
device tree.

Signed-off-by: Mario Jaun <mario.jaun@gmail.com>
2021-04-27 14:16:35 +02:00
Mario Jaun
43ef9013a8 arch: arm: add define REGION_RAM_NOCACHE_ATTR
Add a define for non cachaeable RAM for MPU region definitions.

Signed-off-by: Mario Jaun <mario.jaun@gmail.com>
2021-04-27 14:16:35 +02:00
Mario Jaun
100227cc85 linker: arm: add SRAM3/4 linker section
Add a linker section for SRAM3/4 if it is enabled in the device tree.

Signed-off-by: Mario Jaun <mario.jaun@gmail.com>
2021-04-27 14:16:35 +02:00
Mario Jaun
086c461edb dts: arm: st: h7: define SRAM1-4
Define SRAM1 to SRAM4 memory areas according to the physical memory
organization of the chips.

Signed-off-by: Mario Jaun <mario.jaun@gmail.com>
2021-04-27 14:16:35 +02:00
Ioannis Glaropoulos
cf631fe034 samples: rpmsg_service: use mps2_an521_remote target for remote core
When building and running the rpmsg_service sample on MPS2 AN521
use the mps2_an521_remote target to build the Zephyr image
for the remote core.

Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
2021-04-27 13:40:42 +02:00
Ioannis Glaropoulos
7725699030 samples: openamp: use mps2_an521_remote target for remote core
When building and running the openamp sample on MPS2 AN521,
use the mps2_an521_remote target to build the Zephyr image
for the remote core.

Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
2021-04-27 13:40:42 +02:00