3 commits

Author	SHA1	Message	Date
Tomasz Bursztyka	8e4aff1079	gpio: dw: Support optional clock gating ... This is currently valid for quark_se platform. It's used internally to suspend and/or resume the gpio controller. Change-Id: I5147568ba6b0450363566b5f9fd2e8aa7e41df49 Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>	2016-02-05 20:24:55 -05:00
Tomasz Bursztyka	6351d6671d	quark_se: Exposing only one gpio controller and fixing his bits ... There is no secondary GPIO controller on such SoC. Plus, the unique controller controls at least 28 pins (if not 32, so I set 32), as verified on boards. Change-Id: I61c563671a908551250faa2a0fb9f9e2e17018d3 Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>	2016-02-05 20:24:55 -05:00
Anas Nashif	5115fb57ad	quark_se: rename platform and remove x86 suffix ... Change-Id: I19ac3a4c6081720736c6fbf16b649ccf6ae60e2f Signed-off-by: Anas Nashif <anas.nashif@intel.com>	2016-02-05 20:24:54 -05:00

Renamed from arch/x86/platforms/quark_se-x86/Kconfig (Browse further)