6351d6671d
There is no secondary GPIO controller on such SoC. Plus, the unique controller controls at least 28 pins (if not 32, so I set 32), as verified on boards. Change-Id: I61c563671a908551250faa2a0fb9f9e2e17018d3 Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
181 lines
3.5 KiB
Text
181 lines
3.5 KiB
Text
# Kconfig - Quark SE configuration options
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#
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# Copyright (c) 2015 Intel Corp.
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#
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# Licensed under the Apache License, Version 2.0 (the "License");
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# you may not use this file except in compliance with the License.
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# You may obtain a copy of the License at
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#
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# http://www.apache.org/licenses/LICENSE-2.0
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#
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# Unless required by applicable law or agreed to in writing, software
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# distributed under the License is distributed on an "AS IS" BASIS,
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# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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# See the License for the specific language governing permissions and
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# limitations under the License.
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#
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if PLATFORM_QUARK_SE
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config PLATFORM
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string
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default quark_se
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help
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This option holds the directory name used by the build system to locate
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the correct linker file.
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config PHYS_RAM_ADDR
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default 0xA8006400
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config PHYS_LOAD_ADDR
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default 0x40030000 if XIP
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config RAM_SIZE
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default 55
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config ROM_SIZE
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default 144
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config SYS_CLOCK_HW_CYCLES_PER_SEC
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default 32000000
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config IOAPIC_NUM_RTES
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default 64
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config LOAPIC_TIMER_IRQ
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default 64
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if PINMUX
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config PINMUX_BASE
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default 0xB0800930
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endif
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config DW_AIO_COMPARATOR_BASE_ADDR
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hex
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depends on DW_AIO_COMPARATOR
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default 0xb0800300
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config ARC_INIT
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bool "Quark SE ARC Kickoff"
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default n
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help
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Allows x86 processor to kickoff the ARC slave processor.
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config ARC_INIT_DEBUG
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bool "Allows the usage of GDB with the ARC processor."
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depends on ARC_INIT
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default n
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help
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This option will stop the master processor from boot-strapping
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the ARC slave processor. This will allow GDB to halt and
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engage the ARC processor to proceed step by step execution.
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if GPIO
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config GPIO_DW
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def_bool y
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config GPIO_DW_BOTHEDGES_SUPPORT
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def_bool y
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config GPIO_DW_0
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def_bool y
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config GPIO_DW_0_BASE_ADDR
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default 0xb0000C00
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config GPIO_DW_0_IRQ
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default 8
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config GPIO_DW_0_BITS
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default 32
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endif
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if I2C
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config I2C_DW
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def_bool y
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config I2C_DW_0
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def_bool y
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config I2C_DW_0_BASE
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default 0xb0002800
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config I2C_DW_0_NAME
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default "I2C0"
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config I2C_DW_0_IRQ
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default 0
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config I2C_DW_1
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def_bool y
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config I2C_DW_1_BASE
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default 0xb0002c00
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config I2C_DW_1_NAME
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default "I2C1"
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config I2C_DW_1_IRQ
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default 1
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endif
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if CLOCK_CONTROL
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config CLOCK_CONTROL_QUARK_SE
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def_bool y
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config CLOCK_CONTROL_QUARK_SE_PERIPHERAL
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def_bool y
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config CLOCK_CONTROL_QUARK_SE_PERIPHERAL_DRV_NAME
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default "clk_peripheral"
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config CLOCK_CONTROL_QUARK_SE_EXTERNAL
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def_bool y
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config CLOCK_CONTROL_QUARK_SE_EXTERNAL_DRV_NAME
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default "clk_external"
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config CLOCK_CONTROL_QUARK_SE_SENSOR
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def_bool y
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config CLOCK_CONTROL_QUARK_SE_SENSOR_DRV_NAME
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default "clk_sensor"
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endif
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if SPI
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config SPI_DW
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def_bool y
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config SPI_DW_CLOCK_GATE
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def_bool n
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config SPI_DW_CLOCK_GATE_DRV_NAME
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default CLOCK_CONTROL_QUARK_SE_PERIPHERAL_DRV_NAME
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config SPI_DW_PORT_0
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def_bool y
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config SPI_DW_PORT_0_CLOCK_GATE_SUBSYS
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default 14
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depends on SPI_DW_CLOCK_GATE
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config SPI_DW_PORT_0_REGS
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default 0xb0001000
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config SPI_DW_PORT_0_IRQ
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default 2
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config SPI_DW_PORT_1
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def_bool y
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config SPI_DW_PORT_1_CLOCK_GATE_SUBSYS
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default 15
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depends on SPI_DW_CLOCK_GATE
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config SPI_DW_PORT_1_REGS
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default 0xb0001400
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config SPI_DW_PORT_1_IRQ
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default 3
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endif
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config KERNEL_INIT_PRIORITY_DEFAULT
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default 40
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config KERNEL_INIT_PRIORITY_DEVICE
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default 50
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config UART_CONSOLE_PRIORITY
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default 60
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config IPI_CONSOLE_PRIORITY
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default 60
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config GPIO_DW_INIT_PRIORITY
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default 60
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config I2C_INIT_PRIORITY
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default 60
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endif #PLATFORM_QUARK_SE_X86
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