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quark_se: Exposing only one gpio controller and fixing his bits

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There is no secondary GPIO controller on such SoC. Plus, the unique
controller controls at least 28 pins (if not 32, so I set 32), as
verified on boards.

Change-Id: I61c563671a908551250faa2a0fb9f9e2e17018d3
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
This commit is contained in:
Tomasz Bursztyka 2015-11-27 14:23:02 +01:00 • committed by Anas Nashif
commit 6351d6671d
1 changed files with 1 additions and 10 deletions
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11
arch/x86/platforms/quark_se/Kconfig
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@ -85,16 +85,7 @@ config GPIO_DW_0_BASE_ADDR
config GPIO_DW_0_IRQ
default 8
config GPIO_DW_0_BITS
default 8
config GPIO_DW_1
def_bool y
config GPIO_DW_1_BASE_ADDR
default 0xb0001700
config GPIO_DW_1_IRQ
default 8
config GPIO_DW_0_BITS
default 8
default 32
endif
if I2C