Driver was failing when interrupt mode was enabled for given
instance but interrupt driven TX part was not used. In that
case uart was not disabled after sending a byte which resulted
in continuous interrupt triggering. Added check for
fifo_fill_lock which is set when uart_fifo_fill is used.
Signed-off-by: Krzysztof Chruscinski <krzysztof.chruscinski@nordicsemi.no>
Resetting the dma_tx.buffer_length after the dma_tx.counter
calculation, instead of before.
We need to reset the buffer_length when the transmission is finished,
but in order to give the correct value to the uart_event_tx struct,
we use the dma_tx.buffer_length in the calculation of the
dma_tx.counter, used for the len of the event (number of bytes sent).
I found this problem, when I wanted to use the uart_event_tx.len for
freeing the used space inside a ring buffer (ring_buf_get_finish),
and it didn't work, I logged the values of the uart_event_tx struct,
and found out it always was 0, because the buffer_length was 0,
and the whole buffer was transmitted (stat.pending_length also 0).
Signed-off-by: Prema Jonathan van Win <jonathanvanwin@gmail.com>
In case of the following sequence of UART events:
- UART_ENDRX
- UART_RXRDY
- TIMER_RXTIMEOUT
The application receives one more byte that was received,
due to RX counter alignment upon ENDRX event.
The proposed fix moves the RX byte counter alignment to the
RX timeout event handler.
Signed-off-by: Tomasz Chyrowicz <tomasz.chyrowicz@nordicsemi.no>
If we try and build the MiV uart driver with interrupt support enabled
we get some errors related to code that hasn't been updated. Fix the
compile errors and add SERIAL_SUPPORT_INTERRUPT to the Kconfig to
hopefully catch these issues in the future
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
The context parameter used across device power management is
actually the power state. Just use it and avoid a lot of
unnecessary casts.
Signed-off-by: Flavio Ceolin <flavio.ceolin@intel.com>
This patch add support for polling based UART
on the Renesas R-Car SCIF (Serial Communication Interface
with FIFO)
This hardware block can be found on various Renesas R-Car
SoC series.
It allows to get console on R-Car Gen3 H3ULCB board.
Signed-off-by: Aymeric Aillet <aymeric.aillet@iot.bzh>
Avoid calling PPI driver when enhanced poll functionality is
disabled. Fixing a case when driver failed to compile when
enhanced poll is disabled for all instances.
Signed-off-by: Krzysztof Chruscinski <krzysztof.chruscinski@nordicsemi.no>
NRFX UARTE would write to user supplied buffer on IRQ without checking
whether or not the supplied buffer had available space left to write
one char
Signed-off-by: Arne Edholm <arne.edholm@assaabloy.com>
Automatic collision detection for half-duplex mode can be enabled
by setting `collision-detection` proprety for uart hardware
in the dts file. If the transmitted bit does not match the received
bit an error is raised. This is useful in RS-485 half-duplex mode.
Signed-off-by: Arvin Farahmand <arvinf@ip-logix.com>
Current Cypress PSoC-6 serial driver only works using polling mode.
Add serial driver interrupt routines to allow use of interrupts.
Signed-off-by: Gerson Fernando Budke <gerson.budke@atl-electronics.com>
The current serial driver uses hard code configuration. Rework driver
to use pinctrl and enable full configuration from device tree.
Signed-off-by: Gerson Fernando Budke <gerson.budke@atl-electronics.com>
If there is a UARTE receive error (e.g. framing or break), the RXTO
event may never come. Check error event too, to avoid an infinite loop.
Signed-off-by: Jim Paris <jim@jim.sh>
Replace all existing deprecated API with the recommended alternative.
Fixes#34102
Signed-off-by: Peter Bigot <peter.bigot@nordicsemi.no>
Signed-off-by: Gerson Fernando Budke <nandojve@gmail.com>
With some additional macro-magic we can remove the CMake-based header
file template feature, and instead take advantage of the usual
DT_INST_FOREACH_STATUS_OKAY() macro.
Signed-off-by: Johan Hedberg <johan.hedberg@intel.com>
There are no boards that need hard-coded interrupts so just remove this
build-time conditional branch. The way going forward is that all PCIe
devices should always use PCIE_IRQ_DETECT.
Signed-off-by: Johan Hedberg <johan.hedberg@intel.com>
The structure is now k_work_delayable.
The init function is now k_work_init_delayable.
The submit function is now the k_work_reschedule.
The cancel function is now the k_work_cancel_delayable.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
If we are building the driver with CONFIG_UART_INTERRUPT_DRIVEN=n
we need to ifdef around the decleration of uart_cmsdk_apb_isr()
or we'll get a compiler warning.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
This CL adds support for console expired mechanism. It implements the
notification to power management module that the module for console is
in use. If the interval that module doesn't receive any input message
exceeds CONFIG_SOC_POWER_CONSOLE_EXPIRED_TIMEOUT, the power management
module is allowed to enter deep sleep mode. This mechanism gives a
window in which the users can organize console input.
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
On stm32, the M bits defines the length of the frame between the start
bit and the stop bit, eventually including the parity bit when enabled.
Fix configuration of databits to set correct M bits when parity is
enabled.
This commit tries to address issue zephyrproject-rtos/zephyr#33351
Signed-off-by: Nicolas VINCENT <nicolas.vincent@vossloh.com>
The NRF UARTE has an undocumented feature that when you flush the RX
FIFO, the RXAMOUNT register is not cleared to zero if the FIFO is in
fact empty. This fix is correcting something that was most likely a
typo.
Signed-off-by: Petri Oksanen <petri@iote.ai>
Currently CMSDK uart_irq_is_pending does not use RX and TX interrupt
bits found in INTSTATUS register to check for pending interrutps but
rather it checks for pending interrupts indirectly by checking if RX and
TX buffers are, respectively, full and empty, i.e. it checks bits 0 and
1 in STATE register instead of bits meant for interrupt status found in
INTSTATUS register.
That is particularly problematic because although a RX interrupt implies
a RX buffer full and a TX interrupt implies a TX buffer empty, the
converse is not true. For instance, a TX buffer might be empty for all
data was processed (sent to serial line) already and no further data was
pushed into TX buffer so it remained empty, without generating any
additional TX interrupt. In that case the current uart_irq_is_pending
implementation reports that there are pending interrupts because of the
following logic:
/* Return true if rx buffer full or tx buffer empty */
return (UART_STRUCT(dev)->state & (UART_RX_BF | UART_TX_BF))
!= UART_TX_BF;
which will return 1 (true) if STATE[0] = 0 (TX buffer is empty), since
UART_TX_BF = 1, so STATE[0] != UART_TX_BF, which is true (assuming here
for the sake of simplicity that UART_RX_BF = 0, i.e. RX buffer is empty
too).
One of the common uses of uart_irq_is_pending is in ISR in contructs
like the following:
while (uart_irq_update(dev) && uart_irq_is_pending(dev)) {
if (uart_irq_rx_ready(dev) == 0) { // RX buffer is empty
continue;
}
// RX buffer is full, process RX data
}
So the ISR can be called due to a RX interrupt. Upon finishing
processing the RX data uart_irq_is_pending is called to check for any
pending IRQs and if it happens that TX buffer is empty (like in the case
that TX interrupt is totally disabled) execution gets stuck in the while
loop because TX buffer will never transition to full again, i.e. it will
never have a chance to have STATE[0] = 1, so STATE[0] != UART_TX_BF is
always true.
This commit fixes that undesirable and problematic behavior by making
uart_irq_is_pending use the proper bits in the interrupt status register
(INTSTATUS) to determine if there is indeed any pending interrupts.
That, on the other hand, requires that the pending interrupt flags are
not clearly automatically when calling the ISR, otherwise
uart_irq_is_pending() will return immediatly false on the first call
without any data being really processed inside the ISR. Thus, because
both RX and TX buffer (FIFO) are only 1 byte long, that commit clears
the proper interrupts flags precisely when data is processed (fifo_read
and fifo_fill) or when the interrupts are disabled (irq_rx_disable and
irq_tx_disable).
Finally, that commits also takes the chance to update some comments,
specially regarding the need to "prime" when enabling the TX interrupts
(in uart_cmsdk_apb_irq_tx_enable()). The need to "prime" can be verified
in the CMSDK UART reference implementation in Verilog mentioned in the
"Arm Cortex-M System Design Kit" [0], on p. 4-8, section 4.3,
in cmsdk_apb_uart.v. In that implementation it's also possible to verify
that the FIFO is only 1 byte long, justifying the semantics that if
buffers are not full (STATE[0] or STATE[1] = 0) they are _completly_
empty, holding no data at all.
[0] https://documentation-service.arm.com/static/5e8f1c777100066a414f770b
Signed-off-by: Gustavo Romero <gustavo.romero@linaro.org>
Lowest power consumption can be achieved when uarte peripheral
is disabled when not used. In low power mode, need for both
directions is tracked and if both are no in use peripheral is
disabled. TX disabling is instant but RX requires flushing RX
fifo because data in hardware fifo is lost when peripheral is
re-enabled.
Signed-off-by: Krzysztof Chruscinski <krzysztof.chruscinski@nordicsemi.no>
Refactored driver to prepare for low power extension. Functional
change is limited to handling of RX_DISABLED event which is now
generated from RXTO interrupt context after RX is stopped. Previously,
RX was not stopped after the transfer.
Rx flushing function contains hardware limitation workaround.
Workaround is applied only if flushed data is not discarded.
Signed-off-by: Krzysztof Chruscinski <krzysztof.chruscinski@nordicsemi.no>
Looking at the data sheet for the npcx section 4.15.5 CR_UART Core
Registers, the UICTRL register that is used in the npcx poll
functions is invalid when running in FIFO mode. Instead, calls to
uart_npcx_poll_in and uart_npcx_poll_out should be redirected to
their respective FIFO read/fill functions (when using interrupts).
Changes:
- When calling uart_poll_in: forward the request to uart_fifo_read.
- When calling uart_poll_out: loop until uart_fifo_fill returns
non-0 (we wrote 1 byte).
Signed-off-by: Yuval Peress <peress@chromium.org>
Simple reorg of the function declarations. This change moves
the interrupt driven functions declared at the bottom of the
uart_npcx.c file to the top, clustered under the same ifdef.
Signed-off-by: Yuval Peress <peress@chromium.org>
The stm32 uart driver fails to build on certian platforms due to
changes introduced by:
commit 3c18bcbf77
Author: Francois Ramu <francois.ramu@st.com>
Date: Wed Jan 27 10:27:33 2021 +0100
drivers: serial: stm32 restore uart after lowpower
Fix this by adding some ifdef's around the code that is specific to the
given platforms that the code works on.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Current implementation of uart_npcx_irq_{tx,rx}_ready always returns
false if the respective interrupt enable bit is not set, which means
that the api cannot be used if the interrupts are temporarily disabled
for whatever reasons, breaking patterns such as [1].
Other uart drivers also seems to not have this check, this patch removes
it from the NPCX driver too.
[1] https://github.com/zephyrproject-rtos/zephyr/blob/master/drivers/console/uart_console.c#L549
Signed-off-by: Fabio Baltieri <fabiobaltieri@google.com>
Since the uart device clock will be stopped after ec entered sleep or
deep sleep state and restore its clock automatically, there is no need
to implement code for suspending and resuming devices manually.
The driver still needs to check the current status of uart device when
it wants to change its power state to LOW or SUSPEND power state. It is
crucial to forbid ec enters sleep or deep sleep state when uart device
is busy with transmitting data. Or we will observe broken characters on
the uart console.
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
This CL introduces power management driver that improves the efficiency
of ec operation by adjusting the chip’s power consumption to the level
of activity required by the application in npcx series.
The following list summarizes the main properties of the various chip
power states. Please refer the power.c file for more detail.
Main power states in npcx series include:
- Active: Core, RAM and modules operate at the clocks generated by PLL.
- Idle: Enter this state when the Core executes WFI or WFE instruction.
- Sleep: clock is stopped for most of modules but PLL is enabled.
- Deep Sleep: As Sleep mode but PLL is disabled.
- Standby: All power rails are turned off besides standby and battery
power rails.
And this CL implements one power state, PM_STATE_SUSPEND_TO_IDLE, with
two sub-states for Zephyr power management system.
Sub-state 0 - "Deep Sleep" mode with “Instant” wake-up if residency
time is greater or equal to 1 ms
Sub-state 1 - "Deep Sleep" mode with "Standard" wake-up if residency
time is greater or equal to 201 ms
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
The first uart instance was already devicetree based. To be consistent
convert the second instance to also be devicetree based.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
