drivers: serial: add Renesas R-Car driver
This patch add support for polling based UART on the Renesas R-Car SCIF (Serial Communication Interface with FIFO) This hardware block can be found on various Renesas R-Car SoC series. It allows to get console on R-Car Gen3 H3ULCB board. Signed-off-by: Aymeric Aillet <aymeric.aillet@iot.bzh>
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5 changed files with 319 additions and 0 deletions
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@ -293,6 +293,7 @@
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/drivers/serial/*xmc4xxx* @parthitce
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/drivers/serial/*nuvoton* @ssekar15
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/drivers/serial/*apbuart* @martin-aberg
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/drivers/serial/*rcar* @aaillet
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/drivers/disk/ @jfischer-no
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/drivers/disk/sdmmc_sdhc.h @JunYangNXP
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/drivers/disk/sdmmc_spi.c @JunYangNXP
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@ -38,6 +38,7 @@ zephyr_library_sources_ifdef(CONFIG_UART_XMC4XXX uart_xmc4xxx.c)
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zephyr_library_sources_ifdef(CONFIG_UART_NPCX uart_npcx.c)
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zephyr_library_sources_ifdef(CONFIG_UART_APBUART uart_apbuart.c)
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zephyr_library_sources_ifdef(CONFIG_USB_CDC_ACM ${ZEPHYR_BASE}/misc/empty_file.c)
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zephyr_library_sources_ifdef(CONFIG_UART_RCAR uart_rcar.c)
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zephyr_library_sources_ifdef(CONFIG_USERSPACE uart_handlers.c)
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@ -134,4 +134,6 @@ source "drivers/serial/Kconfig.npcx"
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source "drivers/serial/Kconfig.apbuart"
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source "drivers/serial/Kconfig.rcar"
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endif # SERIAL
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11
drivers/serial/Kconfig.rcar
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11
drivers/serial/Kconfig.rcar
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@ -0,0 +1,11 @@
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# Reneas R-Car UART configuration options
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# Copyright (c) 2021 IoT.bzh
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# SPDX-License-Identifier: Apache-2.0
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config UART_RCAR
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bool "Renesas R-Car UART Driver"
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select SERIAL_HAS_DRIVER
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depends on SOC_FAMILY_RCAR
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help
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Enable Renesas R-Car UART Driver.
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304
drivers/serial/uart_rcar.c
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304
drivers/serial/uart_rcar.c
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@ -0,0 +1,304 @@
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/*
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* Copyright (c) 2021 IoT.bzh
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#define DT_DRV_COMPAT renesas_rcar_scif
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#include <errno.h>
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#include <device.h>
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#include <devicetree.h>
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#include <drivers/uart.h>
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#include <drivers/clock_control.h>
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#include <drivers/clock_control/rcar_clock_control.h>
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struct uart_rcar_cfg {
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uint32_t reg_addr;
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const struct device *clock_dev;
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struct rcar_cpg_clk mod_clk;
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struct rcar_cpg_clk bus_clk;
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};
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struct uart_rcar_data {
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struct uart_config current_config;
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uint32_t clk_rate;
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};
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/* Registers */
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#define SCSMR 0x00 /* Serial Mode Register */
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#define SCBRR 0x04 /* Bit Rate Register */
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#define SCSCR 0x08 /* Serial Control Register */
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#define SCFTDR 0x0c /* Transmit FIFO Data Register */
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#define SCFSR 0x10 /* Serial Status Register */
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#define SCFRDR 0x14 /* Receive FIFO Data Register */
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#define SCFCR 0x18 /* FIFO Control Register */
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#define SCFDR 0x1c /* FIFO Data Count Register */
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#define SCSPTR 0x20 /* Serial Port Register */
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#define SCLSR 0x24 /* Line Status Register */
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#define DL 0x30 /* Frequency Division Register */
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#define CKS 0x34 /* Clock Select Register */
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/* SCSMR (Serial Mode Register) */
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#define SCSMR_C_A BIT(7) /* Communication Mode */
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#define SCSMR_CHR BIT(6) /* 7-bit Character Length */
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#define SCSMR_PE BIT(5) /* Parity Enable */
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#define SCSMR_O_E BIT(4) /* Odd Parity */
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#define SCSMR_STOP BIT(3) /* Stop Bit Length */
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#define SCSMR_CKS1 BIT(1) /* Clock Select 1 */
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#define SCSMR_CKS0 BIT(0) /* Clock Select 0 */
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/* SCSCR (Serial Control Register) */
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#define SCSCR_TEIE BIT(11) /* Transmit End Interrupt Enable */
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#define SCSCR_TIE BIT(7) /* Transmit Interrupt Enable */
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#define SCSCR_RIE BIT(6) /* Receive Interrupt Enable */
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#define SCSCR_TE BIT(5) /* Transmit Enable */
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#define SCSCR_RE BIT(4) /* Receive Enable */
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#define SCSCR_REIE BIT(3) /* Receive Error Interrupt Enable */
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#define SCSCR_TOIE BIT(2) /* Timeout Interrupt Enable */
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#define SCSCR_CKE1 BIT(1) /* Clock Enable 1 */
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#define SCSCR_CKE0 BIT(0) /* Clock Enable 0 */
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/* SCFCR (FIFO Control Register) */
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#define SCFCR_RTRG1 BIT(7) /* Receive FIFO Data Count Trigger 1 */
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#define SCFCR_RTRG0 BIT(6) /* Receive FIFO Data Count Trigger 0 */
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#define SCFCR_TTRG1 BIT(5) /* Transmit FIFO Data Count Trigger 1 */
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#define SCFCR_TTRG0 BIT(4) /* Transmit FIFO Data Count Trigger 0 */
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#define SCFCR_MCE BIT(3) /* Modem Control Enable */
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#define SCFCR_TFRST BIT(2) /* Transmit FIFO Data Register Reset */
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#define SCFCR_RFRST BIT(1) /* Receive FIFO Data Register Reset */
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#define SCFCR_LOOP BIT(0) /* Loopback Test */
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/* SCFSR (Serial Status Register) */
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#define SCFSR_PER3 BIT(15) /* Parity Error Count 3 */
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#define SCFSR_PER2 BIT(14) /* Parity Error Count 2 */
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#define SCFSR_PER1 BIT(13) /* Parity Error Count 1 */
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#define SCFSR_PER0 BIT(12) /* Parity Error Count 0 */
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#define SCFSR_FER3 BIT(11) /* Framing Error Count 3 */
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#define SCFSR_FER2 BIT(10) /* Framing Error Count 2 */
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#define SCFSR_FER_1 BIT(9) /* Framing Error Count 1 */
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#define SCFSR_FER0 BIT(8) /* Framing Error Count 0 */
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#define SCFSR_ER BIT(7) /* Receive Error */
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#define SCFSR_TEND BIT(6) /* Transmission ended */
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#define SCFSR_TDFE BIT(5) /* Transmit FIFO Data Empty */
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#define SCFSR_BRK BIT(4) /* Break Detect */
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#define SCFSR_FER BIT(3) /* Framing Error */
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#define SCFSR_PER BIT(2) /* Parity Error */
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#define SCFSR_RDF BIT(1) /* Receive FIFO Data Full */
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#define SCFSR_DR BIT(0) /* Receive Data Ready */
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/* SCLSR (Line Status Register) on (H)SCIF */
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#define SCLSR_TO BIT(2) /* Timeout */
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#define SCLSR_ORER BIT(0) /* Overrun Error */
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/* Helper macros for UART */
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#define DEV_UART_CFG(dev) \
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((const struct uart_rcar_cfg *)(dev)->config)
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#define DEV_UART_DATA(dev) \
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((struct uart_rcar_data *)(dev)->data)
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static void uart_rcar_write_8(const struct uart_rcar_cfg *config,
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uint32_t offs, uint8_t value)
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{
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sys_write8(value, config->reg_addr + offs);
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}
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static uint16_t uart_rcar_read_16(const struct uart_rcar_cfg *config,
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uint32_t offs)
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{
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return sys_read16(config->reg_addr + offs);
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}
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static void uart_rcar_write_16(const struct uart_rcar_cfg *config,
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uint32_t offs, uint16_t value)
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{
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sys_write16(value, config->reg_addr + offs);
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}
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static void uart_rcar_set_baudrate(const struct device *dev,
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uint32_t baud_rate)
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{
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const struct uart_rcar_cfg *config = DEV_UART_CFG(dev);
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struct uart_rcar_data *data = DEV_UART_DATA(dev);
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uint8_t reg_val;
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reg_val = ((data->clk_rate + 16 * baud_rate) / (32 * baud_rate) - 1);
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uart_rcar_write_8(config, SCBRR, reg_val);
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}
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static int uart_rcar_poll_in(const struct device *dev, unsigned char *p_char)
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{
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const struct uart_rcar_cfg *config = DEV_UART_CFG(dev);
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uint16_t reg_val;
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/* Receive FIFO empty */
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if (!((uart_rcar_read_16(config, SCFSR)) & SCFSR_RDF)) {
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return -1;
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}
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*p_char = uart_rcar_read_16(config, SCFRDR);
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reg_val = uart_rcar_read_16(config, SCFSR);
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reg_val &= ~SCFSR_RDF;
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uart_rcar_write_16(config, SCFSR, reg_val);
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return 0;
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}
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static void uart_rcar_poll_out(const struct device *dev, unsigned char out_char)
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{
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const struct uart_rcar_cfg *config = DEV_UART_CFG(dev);
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uint16_t reg_val;
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/* Wait for empty space in transmit FIFO */
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while (!(uart_rcar_read_16(config, SCFSR) & SCFSR_TDFE)) {
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}
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uart_rcar_write_8(config, SCFTDR, out_char);
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reg_val = uart_rcar_read_16(config, SCFSR);
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reg_val &= ~(SCFSR_TDFE | SCFSR_TEND);
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uart_rcar_write_16(config, SCFSR, reg_val);
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}
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static int uart_rcar_configure(const struct device *dev,
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const struct uart_config *cfg)
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{
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const struct uart_rcar_cfg *config = DEV_UART_CFG(dev);
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struct uart_rcar_data *data = DEV_UART_DATA(dev);
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uint16_t reg_val;
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if (cfg->parity != UART_CFG_PARITY_NONE ||
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cfg->stop_bits != UART_CFG_STOP_BITS_1 ||
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cfg->data_bits != UART_CFG_DATA_BITS_8 ||
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cfg->flow_ctrl != UART_CFG_FLOW_CTRL_NONE) {
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return -ENOTSUP;
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}
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/* Disable Transmit and Receive */
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reg_val = uart_rcar_read_16(config, SCSCR);
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reg_val &= ~(SCSCR_TE | SCSCR_RE);
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uart_rcar_write_16(config, SCSCR, reg_val);
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/* Emptying Transmit and Receive FIFO */
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reg_val = uart_rcar_read_16(config, SCFCR);
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reg_val |= (SCFCR_TFRST | SCFCR_RFRST);
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uart_rcar_write_16(config, SCFCR, reg_val);
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/* Resetting Errors Registers */
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reg_val = uart_rcar_read_16(config, SCFSR);
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reg_val &= ~(SCFSR_ER | SCFSR_DR | SCFSR_BRK | SCFSR_RDF);
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uart_rcar_write_16(config, SCFSR, reg_val);
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reg_val = uart_rcar_read_16(config, SCLSR);
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reg_val &= ~(SCLSR_TO | SCLSR_ORER);
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uart_rcar_write_16(config, SCLSR, reg_val);
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/* Clock selection */
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reg_val = uart_rcar_read_16(config, SCSCR);
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reg_val &= ~(SCSCR_CKE1 | SCSCR_CKE0 | SCSCR_TIE | SCSCR_RIE |
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SCSCR_TE | SCSCR_RE | SCSCR_TOIE);
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uart_rcar_write_16(config, SCSCR, reg_val);
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/* Serial Configuration (8N1) & Clock Source selection */
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reg_val = uart_rcar_read_16(config, SCSMR);
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reg_val &= ~(SCSMR_C_A | SCSMR_CHR | SCSMR_PE | SCSMR_O_E | SCSMR_STOP |
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SCSMR_CKS1 | SCSMR_CKS0);
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uart_rcar_write_16(config, SCSMR, reg_val);
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/* Set baudrate */
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uart_rcar_set_baudrate(dev, cfg->baudrate);
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/* FIFOs data count trigger configuration */
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reg_val = uart_rcar_read_16(config, SCFCR);
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reg_val &= ~(SCFCR_RTRG1 | SCFCR_RTRG0 | SCFCR_TTRG1 | SCFCR_TTRG0 |
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SCFCR_MCE | SCFCR_TFRST | SCFCR_RFRST);
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uart_rcar_write_16(config, SCFCR, reg_val);
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/* Enable Transmit & Receive */
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reg_val = uart_rcar_read_16(config, SCSCR);
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reg_val |= (SCSCR_TE | SCSCR_RE);
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reg_val &= ~(SCSCR_TIE | SCSCR_RIE | SCSCR_TEIE | SCSCR_REIE |
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SCSCR_TOIE);
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uart_rcar_write_16(config, SCSCR, reg_val);
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data->current_config = *cfg;
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return 0;
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}
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static int uart_rcar_config_get(const struct device *dev,
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struct uart_config *cfg)
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{
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struct uart_rcar_data *data = DEV_UART_DATA(dev);
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*cfg = data->current_config;
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return 0;
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}
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static int uart_rcar_init(const struct device *dev)
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{
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const struct uart_rcar_cfg *config = DEV_UART_CFG(dev);
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struct uart_rcar_data *data = DEV_UART_DATA(dev);
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int ret;
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ret = clock_control_on(config->clock_dev,
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(clock_control_subsys_t *)&config->mod_clk);
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if (ret < 0) {
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return ret;
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}
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ret = clock_control_get_rate(config->clock_dev,
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(clock_control_subsys_t *)&config->bus_clk,
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&data->clk_rate);
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if (ret < 0) {
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return ret;
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}
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return uart_rcar_configure(dev, &data->current_config);
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}
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static const struct uart_driver_api uart_rcar_driver_api = {
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.poll_in = uart_rcar_poll_in,
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.poll_out = uart_rcar_poll_out,
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.configure = uart_rcar_configure,
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.config_get = uart_rcar_config_get,
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};
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/* Device Instantiation */
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#define UART_RCAR_INIT(n) \
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static const struct uart_rcar_cfg uart_rcar_cfg_##n = { \
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.reg_addr = DT_INST_REG_ADDR(n), \
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.clock_dev = DEVICE_DT_GET(DT_INST_CLOCKS_CTLR(n)), \
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.mod_clk.module = \
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DT_INST_CLOCKS_CELL_BY_IDX(n, 0, module), \
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.mod_clk.domain = \
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DT_INST_CLOCKS_CELL_BY_IDX(n, 0, domain), \
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.bus_clk.module = \
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DT_INST_CLOCKS_CELL_BY_IDX(n, 1, module), \
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.bus_clk.domain = \
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DT_INST_CLOCKS_CELL_BY_IDX(n, 1, domain), \
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}; \
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\
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static struct uart_rcar_data uart_rcar_data_##n = { \
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.current_config = { \
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.baudrate = DT_INST_PROP(n, current_speed), \
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.parity = UART_CFG_PARITY_NONE, \
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.stop_bits = UART_CFG_STOP_BITS_1, \
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.data_bits = UART_CFG_DATA_BITS_8, \
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.flow_ctrl = UART_CFG_FLOW_CTRL_NONE, \
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}, \
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}; \
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\
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DEVICE_DT_INST_DEFINE(n, \
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uart_rcar_init, \
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NULL, \
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&uart_rcar_data_##n, \
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&uart_rcar_cfg_##n, \
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PRE_KERNEL_1, CONFIG_KERNEL_INIT_PRIORITY_DEVICE, \
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&uart_rcar_driver_api \
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); \
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DT_INST_FOREACH_STATUS_OKAY(UART_RCAR_INIT)
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