This commit adds support for tickless operation on the MIPS CP0 timer.
The code closely follows the Xtensa and RISCV timer drivers.
All tests pass.
Signed-off-by: Remy Luisant <remy@luisant.ca>
Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com>
This commit defines the toolchain command line options for the
Zephyr MIPS architectural port.
Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com>
Signed-off-by: Remy Luisant <remy@luisant.ca>
MIPS (Microprocessor without Interlocked Pipelined Stages) is a
instruction set architecture (ISA) developed by MIPS Computer
Systems, now MIPS Technologies.
This commit provides MIPS architecture support to Zephyr. It is
compatible with the MIPS32 Release 1 specification.
Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com>
Skip re-initialization of statically initialized PDU struct
fields that are not modified at runtime.
When supporting connection oriented CTE, the cp bit and
resv field used for CTE info are modified, hence
re-initialized these and accordingly reset the values
when just-in-time HCI Tx Data fragmentation is performed
in the Lower Link Layer.
Signed-off-by: Vinayak Kariappa Chettimada <vich@nordicsemi.no>
In order to preserve stack, this replaces the single-bus enumeration
loop by a stack based non-recursive pcie hierarchy iteration.
Each stack entry contains a bridge bus enumeration state.
When a bridge endpoint is detected on the current bus, it is
configured and this new bus is pushed on top of the stack in
order to be enumerated at next loop.
When enumeration ends on the bus, the current bus state is
removed from the stack to continue enumeration on the previous
bus.
This enumeration affects a sequential bus number to each new
bus detected in the same order as Linux & U-Boot does.
In this hierarchy:
[0 1 2 ... 31]
| | |
EP | |
| |
[0 1 ... 31] [0 ... 31]
| | |
| EP |
| [0 ... 31]
[0 ... 31] |
| EP
EP
We will get the following BDFs enumeration order:
00:00.0 Endpoint
00:01.0 Bridge => Bus primary 0 secondary 1
01:00.0 Bridge => Bus primary 1 secondary 2
02:00.0 Endpoint
... Bus secondary 2 => subordinate 2
01:01.0 Endpoint
... Bus secondary 1 => subordinate 2
00:02.0 Bridge => Bus primary 0 secondary 3
03:00.0 Bridge => Bus primary 3 secondary 4
04:00.0 Endpoint
... Bus secondary 4 => subordinate 4
... Bus secondary 3 => subordinate 4
The gives the following primary/secondary/subordinate map:
Bus 0 [0 1 2 ... 31]
| | |
| [0:1->2] [0:3->4]
EP 00:00.0 | |
| |
Bus 1 [0 1 ... 31] Bus 3 [0 ... 31]
| | |
| EP 01:01.0 |
[1:2->2] [3:4->4]
| |
| Bus 4 [0 ... 31]
Bus 2 [0 ... 31] |
| EP 04:00.0
EP 02:00.0
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
This adds setup of Type 1 bridge endpoints in two steps, first when
endpoint is detected and secondly when enumerating the next endpoint.
First, the code configures the bus primary & secondary number and 0xff
as subordinate to redirect all PCIe messages to this bus.
Then memory & I/O base are programmed by getting the current allocation
bases.
Finally, now right away, we program the subordinate to the max bus
number under the bridge, here the same, and the memory & I/O limit,
here lower than the base.
This doesn't make the bridge totally usable, enumeration would work
bus not for nested bridges and BARs wouldn't be accessible.
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
In order to prepare support for bridges enumeration, split out the
actual endpoint enumeration code out of the enumeration loop.
Pass a skip_next_func boolean to indicate if the current endpoint
is multifunction of not, to continue to next dev or next function.
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
The Type 1 endpoints has 2 BARs are the same position as the Type 0
BARS 0 & 1, so reuse the generic_pcie_ctrl_type0_enumerate_bars()
for both types by passing the number of possible BARs on the endpoint.
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
When enumerating bridges, the allocated memory base and limit must be
programmed in the bridge config registers.
The base is programmed when starting enumerating the bridge and the
limit is programmed when all endpoints of the bridge and sub-bridges
are enumerated.
Add a second callback to get the base of the next allocation in
order to fill these base & limit values.
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
When a device returns -ENOTSUP for actions TURN_ON or TURN_OFF
the device state still has to be updated since the domain will
cut or restore the energy.
Signed-off-by: Flavio Ceolin <flavio.ceolin@intel.com>
Add an initial demonstration of a physical power domain running on the
`qemu_cortex_m3` platform.
Signed-off-by: Jordan Yates <jordan.yates@data61.csiro.au>
Initial implementation of a simple GPIO controlled power domain.
It exposes no API of its own, all functionality is contained inside
the runtime power management callbacks.
Signed-off-by: Jordan Yates <jordan.yates@data61.csiro.au>
Add a function to tell runtime power management that the device is
starting in the off state instead of active or suspended.
Signed-off-by: Jordan Yates <jordan.yates@data61.csiro.au>
Adds a helper for devices to check if they are on a power-domain or not.
Drivers can use this information to determine if they will be turned on
at some point in the future, or if they are already turned on.
Signed-off-by: Jordan Yates <jordan.yates@data61.csiro.au>
Adds a helper function for running PM actions on child devices. A custom
implementation of `device_supported_foreach` is used as we don't
necessarily want the early exit behaviour of that function in the power
domain context.
The early exit behaviour can be obained through a return value in the
failure callback if that is desired.
Signed-off-by: Jordan Yates <jordan.yates@data61.csiro.au>
Adds `PM_DEVICE_ACTION_TURN_ON` to transition from `PM_DEVICE_STATE_OFF`
to `PM_DEVICE_STATE_SUSPENDED`.
Signed-off-by: Jordan Yates <jordan.yates@data61.csiro.au>
Add a Kconfig symbol to enable/disable power domain on Zephyr.
Disabling power domain save some memory / space.
Signed-off-by: Flavio Ceolin <flavio.ceolin@intel.com>
Add support for power domains on Zephyr. Power domains are implemented
as simple devices so they can use the existent Zephyr API, for resume
and suspend sync and async and also reference count.
The pm subsystem will ensure that domains are resumed before and
suspended after devices using them. For device runtime power
management, every time the device is got or released the same actions
is done to the domain it belongs.
As domains are implemented as simple devices, it is totally acceptable
a domain belongs to another domain.
Signed-off-by: Flavio Ceolin <flavio.ceolin@intel.com>
Add CAN controller error-warning state and document the relationship
between CAN controller states and CAN controller RX/TX error counter
values.
Fixes: #21010
Signed-off-by: Henrik Brix Andersen <hebad@vestas.com>
Some drivers explicitely casted data/config from void * to the
corresponding type. However, this is unnecessary and, in many drivers it
has been misused to drop const qualifier (refer to previous commits).
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
Replace all get_dev_data()/get_dev_config() accessor utilities with
dev->data and dev->config.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
Replace all get_dev_data()/get_dev_config() accessor utilities with
dev->data and dev->config.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
Replace all get_dev_data()/get_dev_config() accessor utilities with
dev->data and dev->config.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
Replace all get_dev_data()/get_dev_config() accessor utilities with
dev->data and dev->config.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
Replace all get_dev_data()/get_dev_config() accessor utilities with
dev->data and dev->config.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
Replace all get_dev_data()/get_dev_config() accessor utilities with
dev->data and dev->config.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
