Zephyr already has various FlexIO drivers but imxrt11xx didn't enable
the base flexio peripheral.
Signed-off-by: Peter van der Perk <peter.vanderperk@nxp.com>
Enable DMIC clock in soc.c - attach to chip's audio PLL. Add pinmux
definitions for the DMIC peripheral. Add nodes to SoC's device tree for
the DMIC peripheral and its audio channels. Configure the DMIC
peripheral in board's device tree to enable audio capture.
Signed-off-by: Vit Stanicek <vit.stanicek@nxp.com>
The "channels-num" should not be used here, other system's parts are using
"channel-count" instead for the same purpose.
Also property's description has been сorrected.
Signed-off-by: Andrey VOLKOV <andrey.volkov@munic.io>
since h750 and h743 have the same irq wkup priority,
we can add wkup interrupt in h743.dsti and simply
include the file in h750.dtsi.
Signed-off-by: Fabrice DJIATSA <fabrice.djiatsa-ext@st.com>
Allows MSTP register addresses to be changed in the device tree
to support different configuration SoCs.
Signed-off-by: TOKITA Hiroshi <tokita.hiroshi@gmail.com>
Background of this modification is to make clock control
driver code provided by Renesas vendor to support for Renesas MCU
on Zephyr.
Signed-off-by: Quy Tran <quy.tran.pz@renesas.com>
Updated the counter_mcux_lptmr driver to support multiple
instances of the lptmr peripheral. Also added a new
binding property to identify if the user is using
counter-mode or pulse mode. since we were previously using the
prescaler value to check this which could be wrong
if used as a division value for getting the freq.
Added a property that allows the user to decide
what the counter value in lptmr should be divided by.
Cleaned up INIT macro for lptmr.
Signed-off-by: Emilio Benavente <emilio.benavente@nxp.com>
dts: arm: nxp: mimxrt1180_evk: add GPT1/2 instance into devicetree
Enable GPT1/2 clock
Add GPT1/GPT2 instances
Set GPT2 as a counter, the default frequency is 240000000
Signed-off-by: Lucien Zhao <lucien.zhao@nxp.com>
This is just the driver for banks 0 to 3. Bank 4 will come via a
separate commit since it needs a different driver.
Signed-off-by: Michael Zimmermann <michael.zimmermann@grandcentrix.net>
This serves two main purposes:
- change the CPU clock via devicetree nodes
- provide the APB frequency to device drivers via the clock driver
interface
Theoretically this could also support choosing between the available
clock sources, but right now we only support LPOSC0 going into PLL0,
going into AHB.
Turning the PLL back off is also not supported since the only current
use case is to set the PLL frequency, turn it on, and switch the AHB
over to it.
Signed-off-by: Michael Zimmermann <michael.zimmermann@grandcentrix.net>
This is the bare minimum and includes the SoC, pinctrl, flash and
devicetree.
I had to include the flash driver that early because I couldn't make
Zephyr compile without flash driver nodes in the device tree.
Signed-off-by: Michael Zimmermann <michael.zimmermann@grandcentrix.net>
Since the clock node is not a child node of the soc node,
but from the root node.
This removes the warning log at compilation.
Signed-off-by: Fabrice DJIATSA <fabrice.djiatsa-ext@st.com>
Initial commit for entropy support on RA8
- drivers: entropy: implementation for TRNG driver of RA8x1
- dts: arm: add device node for trng of RA8x1
- boards: arm: enable support zephyr_entropy for ek_ra8m1 and
update board documentation
Signed-off-by: The Nguyen <the.nguyen.yf@renesas.com>
Signed-off-by: Duy Phuong Hoang. Nguyen <duy.nguyen.xa@renesas.com>
Add definition of the nRF9280 SiP with its Application,
Radio, and Peripheral Processor (PPR) cores and a basic set
of peripherals: GRTC, GPIOs, GPIOTE, and UARTs and few others.
Signed-off-by: Emanuele Di Santo <emdi@nordicsemi.no>
Co-authored-by: Andreas Moltumyr <andreas.moltumyr@nordicsemi.no>
To prepare for supporting flexcan, can node should be
renamed to canxl to support both flexcan and canxl
Signed-off-by: Tu Nguyen Van <tu.nguyenvan@nxp.com>
In SoC imxrt1010, edma channel has separate interrupt entry,
not like the rest of in-tree imxrt SoC series
Signed-off-by: Dat Nguyen Duy <dat.nguyenduy@nxp.com>
add reset control registers information (on RCC_BUS_RSTR LTDCRST bit)
for display peripheral reset.
Signed-off-by: Fabrice DJIATSA <fabrice.djiatsa-ext@st.com>
Add power management support for Apollo3/Apollo3P SPI, and
automatically enables device runtime power management
Signed-off-by: Zhengwei Wang <zwang@ambiq.com>
Add power management support for Apollo3/Apollo3P I2C, and
automatically enables device runtime power management
Signed-off-by: Zhengwei Wang <zwang@ambiq.com>
Add power management support for Apollo3/Apollo3P UART, and
automatically enables device runtime power management
Signed-off-by: Zhengwei Wang <zwang@ambiq.com>
Add initial support for nuvoton npcm400, which is a chip
family of Satellite Management Controller(SMC).
Add ecst python scripts to append the header used by ROM Code
Signed-off-by: Tyrone Ting <kfting@nuvoton.com>
Signed-off-by: James Chiang <cpchiang1@nuvoton.com>
Signed-off-by: Joseph Liu <kwliu@nuvoton.com>
Add lptmr support for ke17z, add related configuration for lptmr
driver.
Add supported CPU power states for idle, stop, partial stop 1, and
partial stop 2.
Signed-off-by: Anke Xiao <anke.xiao@nxp.com>
Add support for the stm32h755 which is a close relative of
the stm32h745 with additional cryptography and hashing
peripherals.
Signed-off-by: Mike Banducci <michael.banducci@sandc.com>
Change NuMaker M463/M467 series USBD clock source to HIRC48M.
This makes core-clock and its clock source PLL not required
to be multiple of 48MHz.
Signed-off-by: Chun-Chieh Li <ccli8@nuvoton.com>
Background of this modification is to make clock control
driver code provided by Renesas vendor to support for Renesas MCU
on Zephyr.
Signed-off-by: Quy Tran <quy.tran.pz@renesas.com>
- Initial support for RA6M2 SoC
Signed-off-by: Tri Nguyen <tri.nguyen.wj@bp.renesas.com>
Signed-off-by: Danh Doan <danh.doan.ue@bp.renesas.com>
Signed-off-by: Duy Phuong Hoang. Nguyen <duy.nguyen.xa@renesas.com>
