boards: s32z2xxdc2: add support for adc
Add devicetree of adc instances for s32z270. Signed-off-by: Ha Duong Quang <ha.duongquang@nxp.com>
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9 changed files with 59 additions and 4 deletions
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@ -55,6 +55,8 @@ The boards support the following hardware features:
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+-----------+------------+-------------------------------------+
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| FLEXCAN | on-chip | can |
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+-----------+------------+-------------------------------------+
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| SAR_ADC | on-chip | adc |
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+-----------+------------+-------------------------------------+
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Other hardware features are not currently supported by the port.
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@ -150,6 +152,15 @@ FlexCAN
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FlexCAN supports CAN Classic (CAN 2.0) and CAN FD modes.
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ADC
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===
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ADC is provided through ADC SAR controller with 2 instances. Each ADC SAR instance has
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12-bit resolution. ADC channels are divided into 2 groups (precision and internal/standard).
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.. note::
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All channels of an instance only run on 1 group channel at the same time.
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Programming and Debugging
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*************************
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@ -50,3 +50,11 @@
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pinctrl-0 = <&flexcan1_default>;
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pinctrl-names = "default";
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};
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&sar_adc0 {
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vref-mv = <1800>;
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};
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&sar_adc1 {
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vref-mv = <1800>;
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};
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@ -16,4 +16,5 @@ supported:
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- can
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- spi
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- counter
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- adc
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vendor: nxp
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@ -16,4 +16,5 @@ supported:
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- can
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- spi
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- counter
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- adc
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vendor: nxp
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@ -16,4 +16,5 @@ supported:
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- can
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- spi
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- counter
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- adc
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vendor: nxp
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@ -16,4 +16,5 @@ supported:
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- can
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- spi
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- counter
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- adc
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vendor: nxp
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@ -1,5 +1,5 @@
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/*
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* Copyright 2023 NXP
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* Copyright 2023-2024 NXP
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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@ -403,6 +403,18 @@ static void adc_nxp_s32_isr(const struct device *dev)
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#define ADC_NXP_S32_GET_INSTANCE(n) \
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LISTIFY(__DEBRACKET ADC_INSTANCE_COUNT, ADC_NXP_S32_INSTANCE_CHECK, (|), n)
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#if (FEATURE_ADC_HAS_HIGH_SPEED_ENABLE == 1U)
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#define ADC_NXP_S32_HIGH_SPEED_CFG(n) .HighSpeedConvEn = DT_INST_PROP(n, high_speed),
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#else
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#define ADC_NXP_S32_HIGH_SPEED_CFG(n)
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#endif
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#if (ADC_SAR_IP_SET_RESOLUTION == STD_ON)
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#define ADC_NXP_S32_RESOLUTION_CFG(n) .AdcResolution = ADC_SAR_IP_RESOLUTION_14,
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#else
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#define ADC_NXP_S32_RESOLUTION_CFG(n)
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#endif
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#define ADC_NXP_S32_INIT_DEVICE(n) \
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ADC_NXP_S32_DRIVER_API(n) \
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ADC_NXP_S32_CALLBACK_DEFINE(n) \
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@ -412,8 +424,8 @@ static void adc_nxp_s32_isr(const struct device *dev)
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static const Adc_Sar_Ip_ConfigType adc_nxp_s32_default_config##n = \
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{ \
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.ConvMode = ADC_SAR_IP_CONV_MODE_ONESHOT, \
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.AdcResolution = ADC_SAR_IP_RESOLUTION_14, \
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.HighSpeedConvEn = DT_INST_PROP(n, high_speed), \
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ADC_NXP_S32_RESOLUTION_CFG(n) \
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ADC_NXP_S32_HIGH_SPEED_CFG(n) \
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.EndOfNormalChainNotification = \
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adc_nxp_s32_normal_endchain_callback##n, \
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.EndOfConvNotification = \
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@ -1074,5 +1074,25 @@
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status = "disabled";
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};
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sar_adc0: adc@402c0000 {
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compatible = "nxp,s32-adc-sar";
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reg = <0x402C0000 0x1000>;
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interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
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<GIC_SPI 169 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
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<GIC_SPI 170 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
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#io-channel-cells = <1>;
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status = "disabled";
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};
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sar_adc1: adc@402e0000 {
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compatible = "nxp,s32-adc-sar";
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reg = <0x402e0000 0x1000>;
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interrupts = <GIC_SPI 201 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
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<GIC_SPI 202 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
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<GIC_SPI 203 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
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#io-channel-cells = <1>;
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status = "disabled";
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};
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};
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};
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2
west.yml
2
west.yml
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@ -198,7 +198,7 @@ manifest:
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groups:
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- hal
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- name: hal_nxp
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revision: e400b5dba27d9abe1403fc799d48b58fa1b1daee
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revision: 00fd3f5a3b1b7fc3a715b1e96cb2d5036b5cc27e
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path: modules/hal/nxp
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groups:
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- hal
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