When using picolibc from the toolchain, we need to use the standard include
paths to make sure the library headers are found, especially for libstdc++.
Add toolchain picolibc to the list of cases for which this is the case.
Signed-off-by: Keith Packard <keithp@keithp.com>
Configure RNG domain clock and align it on USB (as this is the same clk).
This is not stricly required, as this configuration matches default
reset but its more consistent this way.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Similarly to what was done in USB or RNG drivers, configure 48MHz domain
clock using device tree.
By default a freq clock check is enabled.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Remove SDMMC from f410 soc variant since it's not actually available.
Do this in package variant as F410 is included by f412 who has a SDMMC.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Provide SDMMC domain clock, when required (because it is common)use
the same as the one selected by USB and RNG.
Otherwise, when available use HSI48, otherwise use the most handy (MSI,
sysclk ...).
PLLSAI is not used as not implemented for now.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
The RX overrun counter is incremented when the CAN controller receives a
CAN frame matching an installed filter but lacks the capacity to store it
(either due to an already full RX mailbox or a full RX FIFO).
Signed-off-by: Henrik Brix Andersen <hebad@vestas.com>
Fix handling of failed NXP FlexCAN RX mailbox reads. Instead of re-enabling
the RX MB in the ISR, we need to handle a failed RX MB read (e.g. due to a
busy MB bit).
Signed-off-by: Henrik Brix Andersen <hebad@vestas.com>
Add a polling sample for CPU temperature monitor.
This sample demonstrates how to data fetch and print to the console.
Signed-off-by: TOKITA Hiroshi <tokita.hiroshi@fujitsu.com>
Add a locking semaphore so that multiple threads
doing transfers with the same i2c will not produce
unexpected results. The lock will ensure that only one
transfer will happen at a time and it must be completed
before another thread can request a new transfer.
Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
Program the right trim control register for mec150x.
This fixes uart debug console output issue.
Signed-off-by: Jay Vasanth <jay.vasanth@microchip.com>
This change takes advantage of line information coming from new properties
to simplify exti_irq_table definition and isr routing related code.
All __stm32_exti_isr_x routing functions are removed and instead,
stm32_exti_isr is now taking a exti_range structure which provides,
for each irq, start line and range length.
This argument is provided by IRQ_CONNECT macro instead of previous
dev info (which is constant and doesn't need to be provided as argument).
line_range_x variables are generated at driver init thanks to a
mix of dt magic and runtime implementation:
DT_FOREACH_PROP_ELEM iterates over each irq line (counted as
interrupt-names property) call a macro which instantiates populated
line_range_x variables, and calls IRQ_CONNECT for each IRQ.
Additionally, at each iteration stm32_fill_irq_table() is called to
fill exti_irq_table.
Since not required anymore, Kconfig symbols EXTI_STM32_EXTIX_Y_IRQ_PRI
are removed. IRQ prio is now supposed to be configured in device tree.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Add 2 properties in STM32 external interrupt controller:
- num-lines
- line-ranges
Additionally, make interrupt-names a required property.
The properties will help to simplify exti init code in building the
exti_irq_table and simplify the isr related bits.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
sample.yaml was missing a tests section, making it unable to run with
twister. This patch adds the section.
While at that, fix an issue in the sample README.rst.
Fixes#53656.
Signed-off-by: Ederson de Souza <ederson.desouza@intel.com>
During the NVS initialization, if gc had to be done, the NVS cache
rebuild wasn't called.
Signed-off-by: Julien D'Ascenzio <julien.dascenzio@paratronic.fr>
It looks like versions >= 1.9.2 have disappeared from the Sourceforge
website. Since they use GH releases since 1.9.6, the version we use,
let's just update download URL.
Ref. https://github.com/doxygen/doxygen/issues/9801
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
The hda driver uses -EPIPE to signal xrun, as proposed in the alsa lib
https://www.alsa-project.org/alsa-doc/alsa-lib/pcm.html. This commit
changes the xrun error code in dw dma driver from -ENODATA to -EPIPE to
make it consistent across drivers.
Signed-off-by: Adrian Warecki <adrian.warecki@intel.com>
The uart_mux_recv() documentation was wrong, the function parameters
were incorrectly documented.
Signed-off-by: Jukka Rissanen <jukka.rissanen@linux.intel.com>
Given the Zephyr CPU number is no longer tied to the hartid, we must
consider the actual hartid when sending an IPI to a given CPU. Since
those hartids can be anything, let's just save them in the cpu structure
as each CPU is brought online.
While at it, throw in some `get_hart_msip()` cleanups.
Signed-off-by: Nicolas Pitre <npitre@baylibre.com>
Currently it is assumed that Zephyr CPU numbers match their hartid
value one for one. This assumption was relied upon to efficiently
retrieve the current CPU's `struct _cpu` pointer.
People are starting to have systems with a mix of different usage for
each CPU and such assumption may no longer be true.
Let's completely decouple the hartid from the Zephyr CPU number by
stuffing each CPU's `struct _cpu` pointer in their respective scratch
register instead. `arch_curr_cpu()` becomes more efficient as well.
Since the scratch register was previously used to store userspace's
exception stack pointer, that is now moved into `struct _cpu_arch`
which implied minor user space entry code cleanup and rationalization.
Signed-off-by: Nicolas Pitre <npitre@baylibre.com>
There are various call to z_soc_cached_ptr() which returns values
in the cached address space and are stored in temporary variables
that are not marked as in the cached address space. This results
in sparse complaining about discarding the cached address space
attribute. These temporary variables are then passed to other
internal memory management related functions which do not have
the concept of cached address space (as it is currently Xtensa
specific). Because of this, we cannot change the signature of
these functions. Instead, we force a change of address space
when those temporary variables are being assigned to suppress
sparse warnings.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
The argument to arch_xtensa_uncached_ptr() is marked as in
the cached address space. However, when it is being passed to
z_xtropflip(), it is simply casted to uint32_t, thus resulting
in sparse warning about discarding "__cached" address space.
This adds __sparse_force to the cast to suppress the warning.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
While porting the coverage.c file from RIOT to Zephyr, which employs
different compiler flags, I noticed several -Wcast-align GCC warnings on
arm. I think, as is, the current implementation may perform unaligned
memory accesses which may not be supported on certain platforms. To
workaround that, I have rewritten the code for RIOT using
bytewise-writes with `memcpy`.
Signed-off-by: Sören Tempel <tempel@uni-bremen.de>
Implementation ported from TwisterV2.
- quarantine handled by separate module
- multiple yaml allowed from args: --quarantine-list
- scenarios, platforms, architectures keywords in
quarantine yaml are optional, if not given - means take it all
Signed-off-by: Grzegorz Chwierut <grzegorz.chwierut@nordicsemi.no>
To support the repeated start/stop, the stm32 dma driver is
returning 0 if the channel is already started/stopped.
This is not done at the dmamux level if any.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
Full resource names aren't as long as combined basename- and name-buffer
sizes but the compiler doesn't know it. Increasing the buffer size to
avoid the compiler warning.
Signed-off-by: Veijo Pesonen <veijo.pesonen@nordicsemi.no>
Since the event length update is not necessarily an improvement
in all situations a Kconfig option is added so that it can
be disabled for the users that do not need it.
Signed-off-by: Andries Kruithof <andries.kruithof@nordicsemi.no>
Fix the controller implementation to perform connection
event length reservation based on the completed Data Length
Update and/or PHY Update Procedure.
Signed-off-by: Andries Kruithof <andries.kruithof@nordicsemi.no>
The sample documentation mentions that the sample can be built directly
on Linux, which was no longer the case. This commit fixes it.
Signed-off-by: Robert Lubos <robert.lubos@nordicsemi.no>
The old link has expired, the file is no longer avaiable to download.
Update the download link, which now leads to a file in Ubuntu
repositories for the recent LTS release, hopefully making the link valid
for longer period.
As the server ceritficate is signed by a different root CA, update the
root CA as well.
Finally, cleanup how the URL is handled in the sample - for TLS variant
it'll always be provided with a Kconfig, hence no need to repeat it in
the sample.
Signed-off-by: Robert Lubos <robert.lubos@nordicsemi.no>
It's often the case with TLS file servers, that the download link does
not lead to downloaded file, but rather redirects to another server.
Therefore it makes sense to have a minimal support in the sample for
HTTP redirection, so that the file can still be downloaded.
Signed-off-by: Robert Lubos <robert.lubos@nordicsemi.no>
When init_igmp is called the ipv4 pointer was not initialised.
Therefore, a different API needs to be used to ensure that IPv4
is enabled when calling init_igmp.
Fixes#53913
Signed-off-by: Chamira Perera <chamira.perera@audinate.com>
