Commit graph

6 commits

Author SHA1 Message Date
Piotr Zięcik
997a49ade9 arm: userspace: Do not overwrite r7 during syscall.
The r7 register is used as a frame pointer on ARM Thumb. As result, it
cannot be modified by the assembly code in functions using stack frame.

This commit replaces r7 by r8, which is a general purpose register.
Also it fixes #7704.

Signed-off-by: Piotr Zięcik <piotr.ziecik@nordicsemi.no>
2018-06-01 13:07:47 -04:00
Carles Cufi
5b37cd7346 arch: arm: swap: Remove old context switch code
Remove unused context switch code from the helper assembly file that
manages the SuperVisor Call invocations (SVCs). This is no longer in use
in the code, since all calls to __swap() now go through PendSV directly.

Signed-off-by: Carles Cufi <carles.cufi@nordicsemi.no>
2018-05-23 09:34:12 -07:00
Ioannis Glaropoulos
8d1b013f3c arch: arm: thread built-in stack guard implementation
This commit activates the built-in stack guard on the main_thread
before jumping to it upon system initialization. Stack guard is
activated if BUILTIN_STACK_GUARD is enabled by the user. The
commit also activates built-in thread stack guards at every
context switch, if BUILTIN_STACK_GUARD enabled by the user.

Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
2018-05-04 17:26:57 -04:00
Andy Gross
09a8810b33 arm: userspace: Rework system call arguments
This patch changes the ARM system calls to use registers for passing
or arguments.  This removes the possibility of stack issues when
callers do not adhere to the AAPCS.

Fixes #6802

Signed-off-by: Andy Gross <andy.gross@linaro.org>
2018-04-16 10:13:20 -07:00
Leandro Pereira
4d5fbbc517 arch: arm: Flush pipeline after switching privilege levels
During the transition of privilege levels while performing syscalls,
the ARM documentation recommends flushing the pipeline to avoid
pre-fetched instructions from being executed with the previous
privilege level.

The manual says:
   4.16 CONTROL register
   (...) after programming the CONTROL register, an ISB instruction
   should be used.
   (...) This is not implemented in the Cortex M0 processor.

Signed-off-by: Leandro Pereira <leandro.pereira@intel.com>
2018-04-13 15:35:45 -05:00
Andy Gross
cc69d373d1 arch: arm: Change method of __swap processing
This patch reworks the current ARM __swap() function into a C function.
Due to some issues with using svc calls withing fault handlers, we
needed to change the way we initiate a swap by removing the dependence
on svc #0.

Before __swap() is called, the system has already done an irq_lock().
Upon return from __swap(), the equivalent of an irq_lock() is done due
to restoration of the key value from the irq_lock preceeding the call.

For ARM V6M (M0/M0+), the pendsv bit is toggled and the irqs are
enabled.  There is no priority masking in v6m, so it's just a global
enable.  For ARM V7M, the priority mask has to be set to 0x0 to allow
for the pendsv IRQ to be taken.  This is done for both via a call to
irq_unlock(0).

After this unlock, a pendsv irq will be taken, either at the tail end
of the current irq handling if we are in handler mode, or immediately
due to the pendsv being asserted (no other outstanding irqs).  The next
thread will be scheduled.

Upon return from the context switch to the original
thread, the priority mask will already be correct due to the pendsv
processing.

Signed-off-by: Andy Gross <andy.gross@linaro.org>
2018-03-09 21:43:23 -05:00
Renamed from arch/arm/core/swap.S (Browse further)