arch: arm: Change method of __swap processing
This patch reworks the current ARM __swap() function into a C function. Due to some issues with using svc calls withing fault handlers, we needed to change the way we initiate a swap by removing the dependence on svc #0. Before __swap() is called, the system has already done an irq_lock(). Upon return from __swap(), the equivalent of an irq_lock() is done due to restoration of the key value from the irq_lock preceeding the call. For ARM V6M (M0/M0+), the pendsv bit is toggled and the irqs are enabled. There is no priority masking in v6m, so it's just a global enable. For ARM V7M, the priority mask has to be set to 0x0 to allow for the pendsv IRQ to be taken. This is done for both via a call to irq_unlock(0). After this unlock, a pendsv irq will be taken, either at the tail end of the current irq handling if we are in handler mode, or immediately due to the pendsv being asserted (no other outstanding irqs). The next thread will be scheduled. Upon return from the context switch to the original thread, the priority mask will already be correct due to the pendsv processing. Signed-off-by: Andy Gross <andy.gross@linaro.org>
This commit is contained in:
Andy Gross
Anas Nashif
parent
b7de2af1f6
commit
cc69d373d1
3 changed files with 71 additions and 93 deletions
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@ -1,7 +1,8 @@
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zephyr_sources(
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exc_exit.S
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irq_init.c
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swap.S
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swap.c
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swap_helper.S
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fault.c
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irq_manage.c
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thread.c
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69
arch/arm/core/swap.c
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69
arch/arm/core/swap.c
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@ -0,0 +1,69 @@
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/*
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* Copyright (c) 2018 Linaro, Limited
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <kernel.h>
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#include <toolchain.h>
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#include <kernel_structs.h>
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#ifdef CONFIG_EXECUTION_BENCHMARKING
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extern void read_timer_start_of_swap(void);
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#endif
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extern const int _k_neg_eagain;
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/**
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*
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* @brief Initiate a cooperative context switch
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*
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* The __swap() routine is invoked by various kernel services to effect
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* a cooperative context context switch. Prior to invoking __swap(), the caller
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* disables interrupts via irq_lock() and the return 'key' is passed as a
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* parameter to __swap(). The 'key' actually represents the BASEPRI register
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* prior to disabling interrupts via the BASEPRI mechanism.
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*
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* __swap() itself does not do much.
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*
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* It simply stores the intlock key (the BASEPRI value) parameter into
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* current->basepri, and then triggers a PendSV exception, which does
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* the heavy lifting of context switching.
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* This is the only place we have to save BASEPRI since the other paths to
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* __pendsv all come from handling an interrupt, which means we know the
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* interrupts were not locked: in that case the BASEPRI value is 0.
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*
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* Given that __swap() is called to effect a cooperative context switch,
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* only the caller-saved integer registers need to be saved in the thread of the
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* outgoing thread. This is all performed by the hardware, which stores it in
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* its exception stack frame, created when handling the svc exception.
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*
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* On ARMv6-M, the intlock key is represented by the PRIMASK register,
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* as BASEPRI is not available.
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*
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* @return may contain a return value setup by a call to
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* _set_thread_return_value()
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*
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*/
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unsigned int __swap(int key)
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{
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#ifdef CONFIG_USERSPACE
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/* Save off current privilege mode */
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_current->arch.mode = __get_CONTROL() & CONTROL_nPRIV_Msk;
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#endif
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#ifdef CONFIG_EXECUTION_BENCHMARKING
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read_timer_start_of_swap();
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#endif
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/* store off key and return value */
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_current->arch.basepri = key;
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_current->arch.swap_return_value = _k_neg_eagain;
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/* set pending bit to make sure we will take a PendSV exception */
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SCB->ICSR |= SCB_ICSR_PENDSVSET_Msk;
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/* clear mask or enable all irqs to take a pendsv */
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irq_unlock(0);
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return _current->arch.swap_return_value;
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}
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@ -19,7 +19,6 @@
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_ASM_FILE_PROLOGUE
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GTEXT(__swap)
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GTEXT(__svc)
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GTEXT(__pendsv)
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GTEXT(_do_kernel_oops)
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@ -396,94 +395,3 @@ valid_syscall_id:
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#error Unknown ARM architecture
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#endif /* CONFIG_ARMV6_M_ARMV8_M_BASELINE */
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/**
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*
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* @brief Initiate a cooperative context switch
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*
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* The __swap() routine is invoked by various kernel services to effect
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* a cooperative context context switch. Prior to invoking __swap(), the caller
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* disables interrupts via irq_lock() and the return 'key' is passed as a
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* parameter to __swap(). The 'key' actually represents the BASEPRI register
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* prior to disabling interrupts via the BASEPRI mechanism.
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*
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* __swap() itself does not do much.
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*
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* It simply stores the intlock key (the BASEPRI value) parameter into
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* current->basepri, and then triggers a service call exception (svc) to setup
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* the PendSV exception, which does the heavy lifting of context switching.
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* This is the only place we have to save BASEPRI since the other paths to
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* __pendsv all come from handling an interrupt, which means we know the
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* interrupts were not locked: in that case the BASEPRI value is 0.
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*
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* Given that __swap() is called to effect a cooperative context switch,
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* only the caller-saved integer registers need to be saved in the thread of the
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* outgoing thread. This is all performed by the hardware, which stores it in
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* its exception stack frame, created when handling the svc exception.
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*
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* On Cortex-M0/M0+ the intlock key is represented by the PRIMASK register,
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* as BASEPRI is not available.
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*
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* @return may contain a return value setup by a call to
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* _set_thread_return_value()
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*
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* C function prototype:
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*
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* unsigned int __swap (unsigned int basepri);
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*
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*/
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SECTION_FUNC(TEXT, __swap)
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#ifdef CONFIG_EXECUTION_BENCHMARKING
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push {lr}
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bl read_timer_start_of_swap
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#if defined(CONFIG_ARMV6_M_ARMV8_M_BASELINE)
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pop {r3}
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mov lr,r3
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#else
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pop {lr}
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#endif /* CONFIG_ARMV6_M_ARMV8_M_BASELINE */
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#endif /* CONFIG_EXECUTION_BENCHMARKING */
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ldr r1, =_kernel
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ldr r2, [r1, #_kernel_offset_to_current]
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str r0, [r2, #_thread_offset_to_basepri]
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#ifdef CONFIG_USERSPACE
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mrs r0, CONTROL
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movs r3, #1
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ands r0, r3
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str r0, [r2, #_thread_offset_to_mode]
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#endif
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/*
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* Set __swap()'s default return code to -EAGAIN. This eliminates the need
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* for the timeout code to set it itself.
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*/
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ldr r1, =_k_neg_eagain
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ldr r1, [r1]
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str r1, [r2, #_thread_offset_to_swap_return_value]
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#if defined(CONFIG_ARMV6_M_ARMV8_M_BASELINE)
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/* No priority-based interrupt masking on M0/M0+,
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* pending PendSV is used instead of svc
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*/
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ldr r1, =_SCS_ICSR
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ldr r3, =_SCS_ICSR_PENDSV
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str r3, [r1, #0]
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/* Unlock interrupts to allow PendSV, since it's running at prio 0xff
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*
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* PendSV handler will be called if there are no other interrupts
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* of a higher priority pending.
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*/
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cpsie i
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#elif defined(CONFIG_ARMV7_M_ARMV8_M_MAINLINE)
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svc #0
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#else
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#error Unknown ARM architecture
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#endif /* CONFIG_ARMV6_M_ARMV8_M_BASELINE */
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/* coming back from exception, r2 still holds the pointer to _current */
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ldr r0, [r2, #_thread_offset_to_swap_return_value]
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bx lr
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